公开(公告)号：US20180166407A1

公开(公告)日：2018-06-14

申请号：US15892485

申请日：2018-02-09

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Yusheng LIN

IPC: H01L23/00 ,  H01L21/304 ,  H01L21/265 ,  H01L21/324 ,  H01L21/02

CPC classification number: H01L24/05 ,  H01L21/02035 ,  H01L21/26513 ,  H01L21/304 ,  H01L21/324 ,  H01L24/03 ,  H01L24/45 ,  H01L2224/0218 ,  H01L2224/0219 ,  H01L2224/02205 ,  H01L2224/02215 ,  H01L2224/03462 ,  H01L2224/0362 ,  H01L2224/04042 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05184 ,  H01L2224/05582 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/45015 ,  H01L2224/45147 ,  H01L2924/01028 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/07025 ,  H01L2924/1203 ,  H01L2924/13055 ,  H01L2924/2076 ,  H01L2924/00014

Abstract: Implementations of semiconductor packages may include: a silicon die including a pad, the pad including aluminum and copper; a passivation layer over at least a portion of the silicon die and a layer of one of a polyimide (PI) a polybenzoxazole (PBO), or a polymer resin coupled to the passivation layer. The package may include a first copper layer coupled over the pad, the first copper layer being about 1 microns to about 20 microns thick; a second copper layer coupled over the first copper layer, the second copper layer may be about 5 microns to about 40 microns thick; where a width of the first copper layer above the pad may be wider than a width of the second copper layer above the pad. The first and second copper layers may be configured to bond with a heavy copper wire or solder with a copper clip.

公开(公告)号：US20160324008A1

公开(公告)日：2016-11-03

申请号：US15206574

申请日：2016-07-11

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Yusheng LIN ,  Sadamichi TAKAKUSAKI

IPC: H05K3/06

CPC classification number: H05K3/06 ,  C04B37/021 ,  C04B2237/34 ,  C04B2237/343 ,  C04B2237/402 ,  C04B2237/406 ,  C04B2237/407 ,  C04B2237/52 ,  C04B2237/64 ,  C04B2237/82 ,  H01L21/4807 ,  H01L21/4857 ,  H01L21/4871 ,  H01L23/142 ,  H01L23/15 ,  H01L23/3735 ,  H01L23/49822 ,  H01L2924/0002 ,  H05K1/0306 ,  H05K1/0313 ,  H05K1/036 ,  H05K1/056 ,  H05K1/09 ,  H05K3/0011 ,  H05K3/064 ,  H05K3/4644 ,  H05K2201/09736 ,  H01L2924/00

Abstract: A power electronic substrate includes a metallic baseplate having a first and second surface opposing each other. An electrically insulative layer also has first and second surfaces opposing each other, its first surface coupled to the second surface of the metallic baseplate. A plurality of metallic traces each include first and second surfaces opposing each other, their first surfaces coupled to the second surface of the electrically insulative layer. At least one of the metallic traces has a thickness measured along a direction perpendicular to the second surface of the metallic baseplate that is greater than a thickness of another one of the metallic traces also measured along a direction perpendicular to the second surface of the metallic baseplate. In implementations the electrically insulative layer is an epoxy or a ceramic material. In implementations the metallic traces are copper and are plated with a nickel layer at their second surfaces.

公开(公告)号：US20250149450A1

公开(公告)日：2025-05-08

申请号：US19011366

申请日：2025-01-06

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Yusheng LIN ,  Takashi NOMA ,  Francis J. CARNEY

IPC: H01L23/532 ,  H01L23/00

Abstract: Implementations of semiconductor packages may include a die having a first side and a second side opposite the first side, a first metal layer coupled to the first side of the die, a tin layer coupled to the first metal layer, the first metal layer between the die and the tin layer, a backside metal layer coupled to the second side of the die, and a mold compound coupled to the die. The mold compound may cover a plurality of sidewalls of the first metal layer and a plurality of sidewalls of the tin layer and a surface of the mold compound is coplanar with a surface of the tin layer.

公开(公告)号：US20240304603A1

公开(公告)日：2024-09-12

申请号：US18668408

申请日：2024-05-20

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Jinchang ZHOU ,  Yusheng LIN ,  Mingjiao LIU

IPC: H01L25/07 ,  H01L23/00 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065 ,  H01L25/11 ,  H01L29/739 ,  H10N30/50

CPC classification number: H01L25/071 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/09 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/072 ,  H01L25/074 ,  H01L25/117 ,  H01L25/50 ,  H01L29/7395 ,  H10N30/50 ,  H01L23/5385 ,  H01L2224/0401 ,  H01L2224/05085 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2224/1403 ,  H01L2224/29139 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81815 ,  H01L2224/83815 ,  H01L2224/8384 ,  H01L2224/92242 ,  H01L2225/06503 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06572 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/19105

Abstract: A semiconductor device has an interposer including a plurality of conductive vias formed through the interposer. A first semiconductor die is disposed over the interposer. A second semiconductor die is disposed over a first substrate. The first semiconductor die and second semiconductor die are power semiconductor devices. The interposer is disposed over the second semiconductor die opposite the first substrate. A second substrate is disposed over the first semiconductor die opposite the interposer. The first substrate and second substrate provide heat dissipation from the first semiconductor die and second semiconductor die from opposite sides of the semiconductor device. A plurality of first and second interconnect pads is formed in a pattern over the first semiconductor die and second semiconductor die. The second interconnect pads have a different area than the first interconnect pads to aid with alignment when stacking the assembly.

公开(公告)号：US20240030122A1

公开(公告)日：2024-01-25

申请号：US17813380

申请日：2022-07-19

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Yong LIU ,  Yusheng LIN ,  Jerome TEYSSEYRE

IPC: H01L23/498 ,  H01L23/367 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L23/367 ,  H01L24/32 ,  H01L24/33 ,  H01L24/29 ,  H01L24/30 ,  H01L23/3735

Abstract: A substrate includes a ceramic tile and a three-dimensional (3D) conductive structure. The 3D conductive structure includes a planar base layer having a bottom surface bonded to a top surface of the ceramic tile, and a block disposed above the planar base layer. The block is monolithically integrated with the planar base layer. A top surface of the block is configured as a die attach pad. The planar base layer has a base vertical thickness from the top surface of the ceramic tile to a top surface of the planar base layer. The block and the planar base layer have a combined vertical thickness from the top surface of the ceramic tile to a top surface of the block that is greater than the base vertical thickness.

公开(公告)号：US20230352525A1

公开(公告)日：2023-11-02

申请号：US18340650

申请日：2023-06-23

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Peter MOENS ,  Gordon M. GRIVNA ,  Yusheng LIN

IPC: H01L29/06 ,  H01L25/07 ,  H01L29/20 ,  H01L21/762

CPC classification number: H01L29/0649 ,  H01L25/071 ,  H01L29/2003 ,  H01L21/76224

Abstract: In a general aspect, a semiconductor device assembly includes a first portion of a semiconductor substrate; a second portion of the semiconductor substrate, and a semiconductor device layer disposed on the first portion of the semiconductor substrate and the second portion of the semiconductor substrate. The semiconductor device layer includes a first semiconductor device disposed on the first portion of the semiconductor substrate, and a second semiconductor device disposed on the second portion of the semiconductor substrate. The assembly also includes an isolation trench defined in the semiconductor substrate that has a dielectric material disposed therein. The isolation trench is disposed between the first portion of the semiconductor substrate and the second portion of the semiconductor substrate, and electrically isolates the first portion of the semiconductor substrate from the second portion of the semiconductor substrate. The semiconductor device layer excludes the isolation trench.

公开(公告)号：US20230063200A1

公开(公告)日：2023-03-02

申请号：US17822405

申请日：2022-08-25

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Weng-Jin WU ,  Yusheng LIN

IPC: H01L27/146 ,  H01L23/00

Abstract: A method includes disposing a sheet of glass on a front side of a semiconductor substrate that includes at least one image sensor die, attaching the sheet of glass to the at least one image sensor die by a bead of adhesive material disposed on an edge of the at least one image sensor die, and sawing the semiconductor substrate from a back side to form a trench along a side of the at least one image sensor die. The trench extends through a thickness of the semiconductor substrate and through a part of a thickness of the sheet of glass. The method further includes filling the trench with a molding material to form a layer of molding material on a sidewall of the at least one image sensor die, and singulating the semiconductor substrate to isolate an individual image sensor package enclosing the at least one image sensor die.

公开(公告)号：US20220369468A1

公开(公告)日：2022-11-17

申请号：US17816144

申请日：2022-07-29

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Yusheng LIN ,  Sadamichi TAKAKUSAKI

IPC: H05K3/06 ,  H05K1/03 ,  H01L23/14 ,  H01L21/48 ,  H05K1/09 ,  H05K3/46 ,  H05K3/00 ,  H01L23/15 ,  H05K1/05 ,  C04B37/02 ,  H01L23/373

Abstract: A power electronic substrate includes a metallic baseplate having a first and second surface opposing each other. An electrically insulative layer also has first and second surfaces opposing each other, its first surface coupled to the second surface of the metallic baseplate. A plurality of metallic traces each include first and second surfaces opposing each other, their first surfaces coupled to the second surface of the electrically insulative layer. At least one of the metallic traces has a thickness measured along a direction perpendicular to the second surface of the metallic baseplate that is greater than a thickness of another one of the metallic traces also measured along a direction perpendicular to the second surface of the metallic baseplate. In implementations the electrically insulative layer is an epoxy or a ceramic material. In implementations the metallic traces are copper and are plated with a nickel layer at their second surfaces.

公开(公告)号：US20210118774A1

公开(公告)日：2021-04-22

申请号：US16949130

申请日：2020-10-15

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Yusheng LIN ,  Jerome TEYSSEYRE ,  Huibin CHEN

IPC: H01L23/492 ,  H01L23/14 ,  H01L23/498 ,  H01L21/48

Abstract: A method includes disposing a plurality of active solder pads and at least one mechanical support solder pad on the substrate. The plurality of active solder pads provide areas for mechanical bonding of the substrate to at least one device contact pad disposed on a semiconductor die. The at least one mechanical support solder pad provides an area for mechanical bonding of the substrate to at least one dummy device contact pad disposed on the semiconductor die. The method further includes mechanically bonding the substrate to the semiconductor die by forming solder joints between the plurality of active solder pads and the at least one device contact pad, and between the at least one mechanical support pad and the at least one dummy device contact pad.

公开(公告)号：US20210035956A1

公开(公告)日：2021-02-04

申请号：US16678039

申请日：2019-11-08

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Chee Hiong CHEW ,  Atapol PRAJUCKAMOL ,  Stephen ST. GERMAIN ,  Yusheng LIN

IPC: H01L25/07 ,  H01L25/00 ,  H01L23/00 ,  H01L23/367

Abstract: Implementations of semiconductor packages may include: a first substrate having two or more die coupled to a first side, a clip coupled to each of the two or more die on the first substrate and a second substrate having two or more die coupled to a first side of the second substrate. A clip may be coupled to each of the two or more die on the second substrate. The package may include two or more spacers coupled to the first side of the first substrate and a lead frame between the first substrate and the second substrate and a molding compound. A second side of each of the first substrate and the second substrate may be exposed through the molding compound. A perimeter of the first substrate and a perimeter of the second substrate may not fully overlap when coupled through the two or more spacers.