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    Semiconductor Device and Method of Forming Embedded Conductive Layer for Power/Ground Planes in FO-EWLB
    52.
    发明申请
    Semiconductor Device and Method of Forming Embedded Conductive Layer for Power/Ground Planes in FO-EWLB 有权
    在FO-EWLB中形成电源/接地平面的嵌入式导电层的半导体器件和方法

    公开(公告)号：US20140252573A1

    公开(公告)日：2014-09-11

    申请号：US14193267

    申请日：2014-02-28

    Applicant: STATS ChipPAC, Ltd.

    Inventor： Yaojian Lin ,  Xu Sheng Bao ,  Kang Chen

    IPC: H01L23/495 ,  H01L21/48

    CPC classification number: H01L21/485 ,  H01L21/568 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/00 ,  H01L2924/00012

    Abstract: A semiconductor device has a first conductive layer and a semiconductor die disposed adjacent to the first conductive layer. An encapsulant is deposited over the first conductive layer and semiconductor die. An insulating layer is formed over the encapsulant, semiconductor die, and first conductive layer. A second conductive layer is formed over the insulating layer. A first portion of the first conductive layer is electrically connected to VSS and forms a ground plane. A second portion of the first conductive layer is electrically connected to VDD and forms a power plane. The first conductive layer, insulating layer, and second conductive layer constitute a decoupling capacitor. A microstrip line including a trace of the second conductive layer is formed over the insulating layer and first conductive layer. The first conductive layer is provided on an embedded dummy die, interconnect unit, or modular PCB unit.

    Abstract translation: 半导体器件具有邻近第一导电层设置的第一导电层和半导体管芯。 密封剂沉积在第一导电层和半导体管芯上。 绝缘层形成在密封剂，半导体管芯和第一导电层之上。 在绝缘层上形成第二导电层。 第一导电层的第一部分电连接到VSS并形成接地平面。 第一导电层的第二部分电连接到VDD并形成电源平面。 第一导电层，绝缘层和第二导电层构成去耦电容器。 在绝缘层和第一导电层上形成包括第二导电层的迹线的微带线。 第一导电层设置在嵌入的虚设裸片，互连单元或模块化PCB单元上。

    Method of forming top electrode for capacitor and interconnection in integrated passive device (IPD)
    55.
    发明授权
    Method of forming top electrode for capacitor and interconnection in integrated passive device (IPD) 有权
    在集成无源器件（IPD）中形成电容器和互连顶电极的方法

    公开(公告)号：US08703548B2

    公开(公告)日：2014-04-22

    申请号：US13765478

    申请日：2013-02-12

    Applicant: STATS ChipPAC, Ltd.

    Inventor： Yaojian Lin ,  Robert C. Frye

    IPC: H01L21/339

    CPC classification number: H01L28/40 ,  H01L23/5223 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105

    Abstract: A method of manufacturing a semiconductor device includes providing a substrate having a first conductive layer disposed on a top surface of the substrate. A high resistivity layer is formed over the substrate and the first conductive layer. A dielectric layer is deposited over the substrate, first conductive layer and high resistivity layer. A portion of the dielectric layer, high resistivity layer, and first conductive layer forms a capacitor stack. A first passivation layer is formed over the dielectric layer. A second conductive layer is formed over the capacitor stack and a portion of the first passivation layer. A first opening is etched in the dielectric layer to expose a surface of the high resistivity layer. A third and fourth conductive layer is deposited over the first opening in the dielectric layer and a portion of the first passivation layer.

    Abstract translation: 一种制造半导体器件的方法包括提供具有设置在基板的顶表面上的第一导电层的基板。 在基板和第一导电层上形成高电阻率层。 介电层沉积在衬底，第一导电层和高电阻率层上。 介电层，高电阻率层和第一导电层的一部分形成电容器叠层。 在电介质层上形成第一钝化层。 在电容器堆叠和第一钝化层的一部分上形成第二导电层。 在电介质层中蚀刻第一开口以暴露高电阻率层的表面。 在电介质层中的第一开口和第一钝化层的一部分上沉积第三和第四导电层。

    Semiconductor Device Having Balanced Band-Pass Filter Implemented with LC Resonators
    56.
    发明申请
    Semiconductor Device Having Balanced Band-Pass Filter Implemented with LC Resonators 有权
    具有平衡带通滤波器的半导体器件用LC谐振器实现

    公开(公告)号：US20140002207A1

    公开(公告)日：2014-01-02

    申请号：US14018282

    申请日：2013-09-04

    Applicant: STATS ChipPAC, Ltd.

    Inventor： Kai Liu ,  Robert C. Frye ,  Yaojian Lin

    IPC: H03H7/42 ,  H01L49/02

    CPC classification number: H03H7/422 ,  H01L28/10 ,  H03H7/09 ,  H03H7/1766 ,  H03H7/42

    Abstract: A band-pass filter has a plurality of frequency band channels each including a first inductor having a first terminal coupled to a first balanced port and a second terminal coupled to a second balanced port. A first capacitor is coupled between the first and second terminals of the first inductor. A second inductor has a first terminal coupled to a first unbalanced port and a second terminal coupled to a second unbalanced port. The second inductor is disposed within a first distance of the first inductor to induce magnetic coupling. A second capacitor is coupled between the first and second terminals of the second inductor. A third inductor is disposed within a second distance of the first inductor and within a third distance of the second inductor to induce magnetic coupling. A second capacitor is coupled between first and second terminals of the third inductor.

    Abstract translation: 带通滤波器具有多个频带信道，每个频带信道包括具有耦合到第一平衡端口的第一端子的第一电感器和耦合到第二平衡端口的第二端子。 第一电容器耦合在第一电感器的第一和第二端子之间。 第二电感器具有耦合到第一不平衡端口的第一端子和耦合到第二不平衡端口的第二端子。 第二电感器设置在第一电感器的第一距离内以引起磁耦合。 第二电容器耦合在第二电感器的第一和第二端子之间。 第三电感器设置在第一电感器的第二距离内并且在第二电感器的第三距离内，以引起磁耦合。 第二电容器耦合在第三电感器的第一和第二端子之间。

    Semiconductor device and method of forming dual fan-out semiconductor package
    60.
    发明授权
    Semiconductor device and method of forming dual fan-out semiconductor package 有权

    公开(公告)号：US10418298B2

    公开(公告)日：2019-09-17

    申请号：US14035726

    申请日：2013-09-24

    Applicant: STATS ChipPac, Ltd.

    Inventor： Yaojian Lin

    IPC: H01L23/31 ,  H01L23/00 ,  H01L23/538 ,  H01L21/56

    Abstract: A semiconductor device has a semiconductor die with a first encapsulant disposed over the semiconductor die. A first build-up interconnect structure is formed over the semiconductor die and first encapsulant. The first build-up interconnect structure has a first conductive layer. The first conductive layer includes a plurality of first conductive traces. A second encapsulant is disposed over the semiconductor die and the first build-up interconnect structure. A second build-up interconnect structure is formed over the first build-up interconnect structure and the second encapsulant. The second build-up interconnect structure has a second conductive layer. The second conductive layer includes a plurality of second conductive traces. A distance between the second conductive traces is greater than a distance between the first conductive traces. A passive device is disposed within the first encapsulant and/or the second encapsulant. A plurality of conductive vias is disposed in the first encapsulant and/or the second encapsulant.

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