公开(公告)号：US20070139848A1

公开(公告)日：2007-06-21

申请号：US11679064

申请日：2007-02-26

Applicant: Edwin Harris ,  Tushar Vyas ,  Timothy Pachla

Inventor： Edwin Harris ,  Tushar Vyas ,  Timothy Pachla

IPC: H02H9/06

CPC classification number: H01C7/12 ,  H01G2/14 ,  H02H9/044 ,  H05K1/0257 ,  H05K1/0259 ,  H05K1/0298 ,  H05K1/0393 ,  H05K1/167 ,  H05K3/28 ,  H05K2201/0738 ,  H05K2201/09763

Abstract: A first voltage variable material (“VVM”) includes an insulative binder, first conductive particles with a core and a shell held in the insulating binder and second conductive particles without a shell held in the insulating binder; a second VVM includes an insulating binder, first conductive particles with a core and a shell held in the insulating binder, second conductive particles without a shell held in the insulating binder, and semiconductive particles with a core and a shell held in the insulating binder; a third VVM includes only first conductive particles with a core and a shell held in the insulating binder.

Abstract translation: 第一电压可变材料（“VVM”）包括绝缘粘合剂，具有芯和保持在绝缘粘合剂中的壳的第一导电颗粒和没有保持在绝缘粘合剂中的壳的第二导电颗粒; 第二VVM包括绝缘粘合剂，具有芯和保持在绝缘粘合剂中的壳的第一导电颗粒，没有保持在绝缘粘合剂中的壳的第二导电颗粒和保持在绝缘粘合剂中的芯和壳的半导体颗粒; 第三VVM仅包括具有芯和保持在绝缘粘合剂中的壳的第一导电颗粒。

公开(公告)号：US07218492B2

公开(公告)日：2007-05-15

申请号：US10944124

申请日：2004-09-17

Applicant: Karen Pamelia Shrier

Inventor： Karen Pamelia Shrier

IPC: H02H9/00

CPC classification number: H05K1/0256 ,  H01C7/10 ,  H01C7/13 ,  H01C7/18 ,  H01L2224/48091 ,  H01L2924/00014 ,  H05K1/0259 ,  H05K1/167 ,  H05K1/185 ,  H05K3/429 ,  H05K2201/0738 ,  H01L2224/45099

Abstract: A device (10) for suppressing electrostatic discharge comprises first and second multilayer structures (14, 16) surrounding an electrostatic discharge reactance layer (12), the resistance of said electrostatic discharge reactance layer (12) varying in response to the occurrence of an electrostatic discharge signal. Each multilayer structure (14, 16) comprises a barrier layer (18), a terminal layer (20) and an electrode layer (28). Alternatively, a conductive layer (80) can be used instead of a second multilayer structure (16). An ESD suppression device (110) can be embedded in a printed circuit board (122, 210) providing a way to protect board components from harmful ESD events.

Abstract translation: 用于抑制静电放电的装置（10）包括围绕静电放电电抗层（12）的第一和第二多层结构（14,16），所述静电放电电抗层（12）的电阻响应于静电发生而变化 放电信号。 每个多层结构（14,16）包括阻挡层（18），端子层（20）和电极层（28）。 或者，可以使用导电层（80）代替第二多层结构（16）。 ESD抑制装置（110）可嵌入印刷电路板（122,210）中，从而提供保护电路板部件免受有害ESD事件的影响。

公开(公告)号：US07132922B2

公开(公告)日：2006-11-07

申请号：US10746020

申请日：2003-12-23

Applicant: Edwin James Harris ,  Tushar Vyas ,  Stephen J. Whitney

Inventor： Edwin James Harris ,  Tushar Vyas ,  Stephen J. Whitney

IPC: H01C7/10

CPC classification number: H01L23/62 ,  H01C17/06513 ,  H01C17/06553 ,  H01C17/0656 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/3011 ,  H02H9/044 ,  H05K1/0257 ,  H05K1/0298 ,  H05K1/167 ,  H05K2201/0224 ,  H05K2201/0272 ,  H05K2201/0738 ,  H01L2924/00

Abstract: A voltage variable material (“VVM”) including an insulative binder that is formulated to intrinsically adhere to conductive and non-conductive surfaces is provided. The binder and thus the VVM is self-curable and applicable in a spreadable form that dries before use. The binder eliminates the need to place the VVM in a separate device or to provide separate printed circuit board pads on which to electrically connect the VVM. The binder and thus the VVM can be directly applied to many different types of substrates, such as a rigid (FR-4) laminate, a polyimide or a polymer. The VVM can also be directly applied to different types of substrates that are placed inside a device. In one embodiment, the VVM includes doped semiconductive particles having a core, such which can be silicon, and an inert coating, which can be an oxide. The particles are mixed in the binder with conductive particles.

Abstract translation: 提供了包括被配制为固有地粘附到导电和非导电表面的绝缘粘合剂的电压可变材料（“VVM”）。 粘合剂，因此VVM是可自我修复的，并且可以在使用前干燥的可涂抹形式使用。 粘合剂消除了将VVM放置在单独的装置中的需要，或者提供用于电连接VVM的单独的印刷电路板焊盘。 粘合剂，因此VVM可以直接应用于许多不同类型的基材，例如刚性（FR-4）层压材料，聚酰亚胺或聚合物。 VVM也可以直接应用于放置在设备内部的不同类型的基板。 在一个实施例中，VVM包括具有芯的掺杂的半导体颗粒，其可以是硅，以及可以是氧化物的惰性涂层。 颗粒在粘合剂中与导电颗粒混合。

公开(公告)号：US20060181827A1

公开(公告)日：2006-08-17

申请号：US11357618

申请日：2006-02-16

Applicant: George Dudnikov ,  Franz Gisin ,  Gregory Schroeder

Inventor： George Dudnikov ,  Franz Gisin ,  Gregory Schroeder

IPC: H02H9/00

CPC classification number: H05K1/0257 ,  H01L23/62 ,  H01L2924/0002 ,  H05K1/0259 ,  H05K1/0298 ,  H05K1/167 ,  H05K2201/0738 ,  H05K2201/09309 ,  H01L2924/00

Abstract: Protection for sensitive components on a printed circuit board by selectively depositing transient protection material on one or more layers of the printed circuit board is disclosed.

公开(公告)号：US20060151755A1

公开(公告)日：2006-07-13

申请号：US11371120

申请日：2006-03-08

Applicant: Chi-Ming Chan ,  Kai-Mo Ng ,  Catherine Wong ,  Ying Cheung

Inventor： Chi-Ming Chan ,  Kai-Mo Ng ,  Catherine Wong ,  Ying Cheung

IPC: H01B1/12

CPC classification number: H01B1/22 ,  H05K1/0257 ,  H05K1/0259 ,  H05K1/167 ,  H05K2201/0738 ,  Y10T428/257 ,  Y10T428/31663

Abstract: The invention provides a process for preparing an overvoltage protection material comprising: (i) preparing a mixture comprising a polymer binder precursor and a conductive material; and (ii) heating the mixture to cause reaction of the polymer binder precursor and generate a polymer matrix having conductive material dispersed therein, wherein the polymer binder precursor is chosen such that substantially no solvent is generated during the reaction.

公开(公告)号：US07035072B2

公开(公告)日：2006-04-25

申请号：US10192314

申请日：2002-07-10

Applicant: James A. Colby

Inventor： James A. Colby

IPC: H01C7/10 ,  H01C7/12 ,  H01C7/13 ,  H02H1/04

CPC classification number: H05K9/0066 ,  H01R13/6485 ,  H01R13/6666 ,  H02H9/04 ,  H04M3/18 ,  H05K1/0259 ,  H05K1/0393 ,  H05K1/162 ,  H05K1/167 ,  H05K1/18 ,  H05K2201/0738 ,  H05K2201/10015 ,  H05K2201/10022

Abstract: The present invention provides an ESD apparatus that includes an electrical overstress suppression device in series with a capacitor. The ESD apparatus is ideally suited for use with network communication devices, but any electronic device requiring overvoltage protection and isolation may employ the ESD apparatus of the present invention. In one embodiment, the ESD apparatus includes a capacitor and an electrical overstress protection device that electrically communicates in series with the capacitor. In another embodiment, the ESD apparatus includes an electrical overstress protection device having a voltage variable material and a capacitor that electrically communicates in series with the overstress protection device. The capacitor is sized so that the overstress device can withstand an application of a predetermined steady state voltage.

公开(公告)号：US07034652B2

公开(公告)日：2006-04-25

申请号：US10192034

申请日：2002-07-10

Applicant: Stephen J. Whitney ,  Hugh Hyatt ,  Louis Rector

Inventor： Stephen J. Whitney ,  Hugh Hyatt ,  Louis Rector

IPC: H01C8/00

CPC classification number: H05K1/0246 ,  H01C7/105 ,  H01C7/118 ,  H01C7/12 ,  H05K1/0259 ,  H05K1/095 ,  H05K1/167 ,  H05K3/284 ,  H05K2201/0738 ,  H05K2201/10022 ,  H05K2201/10636 ,  Y02P70/611

Abstract: The present invention provides a multifunction resistor having an improved voltage variable material (“VVM”). More specifically, the present invention provides a polymer VVM that has been formulated with a high percentage loading of conductive and/or semiconductive particles. A known length of the relatively conductive VVM is placed between adjacent electrodes to produce a desired Ohmic normal state resistance. When an electrostatic discharge event occurs, the VVM of the multifunctional resistor becomes highly conductive and dissipates the ESD threat. One application for this “resistor” is the termination of a transmission line, which prevents unwanted reflections and distortion of high frequency signals.

公开(公告)号：US20050057867A1

公开(公告)日：2005-03-17

申请号：US10958442

申请日：2004-10-05

Applicant: Edwin Harris ,  Tushar Vyas ,  Timothy Pachla ,  James Colby

Inventor： Edwin Harris ,  Tushar Vyas ,  Timothy Pachla ,  James Colby

IPC: H02H9/04 ,  H05K1/00 ,  H05K1/02 ,  H05K1/16 ,  H02H9/00

CPC classification number: H01C7/12 ,  H01G2/14 ,  H02H9/044 ,  H05K1/0257 ,  H05K1/0259 ,  H05K1/0298 ,  H05K1/0393 ,  H05K1/167 ,  H05K3/28 ,  H05K2201/0738 ,  H05K2201/09763

Abstract: A voltage variable material (“VVM”) including an insulative binder that is formulated to intrinsically adhere to conductive and non-conductive surfaces is provided. The binder and thus the VVM is self-curable and applicable in a spreadable form that dries before use. The binder eliminates the need to place the VVM in a separate device or to provide separate printed circuit board pads on which to electrically connect the VVM. The binder and thus the VVM can be directly applied to many different types of substrates, such as a rigid FR-4 laminate, a polyimide, a polymer or a multilayer PCB via a process such as screen or stencil printing. In one embodiment, the VVM includes two types of conductive particles, one with a core and one without a core. The VVM can also have core-shell type semiconductive particles.

Abstract translation: 提供了包括被配制为固有地粘附到导电和非导电表面的绝缘粘合剂的电压可变材料（“VVM”）。 粘合剂和因此VVM是自固化型和适用在使用前，其干燥可涂抹的形式。 粘合剂消除了将VVM放置在单独的装置中的需要，或者提供用于电连接VVM的单独的印刷电路板焊盘。 粘合剂和因此的VVM可以通过诸如筛网或模版印刷的工艺直接应用于许多不同类型的基材，例如刚性FR-4层压板，聚酰亚胺，聚合物或多层PCB。 在一个实施例中，VVM包括两种类型的导电颗粒，其中一个芯和一个没有芯。 VVM还可以具有核 - 壳型半导体颗粒。

公开(公告)号：US06570765B2

公开(公告)日：2003-05-27

申请号：US10013952

申请日：2001-12-13

Applicant: Gerald R. Behling ,  James B. Intrater

Inventor： Gerald R. Behling ,  James B. Intrater

IPC: H05K720

CPC classification number: H01T4/08 ,  H01L23/60 ,  H01L23/62 ,  H01L2224/16225 ,  H01L2924/09701 ,  H05K1/0259 ,  H05K1/026 ,  H05K1/111 ,  H05K1/116 ,  H05K1/167 ,  H05K2201/0738 ,  H05K2201/09781 ,  H05K2201/10689 ,  H05K2201/10704 ,  H05K2201/10734

Abstract: Over voltage protection is provided for electronic circuits by disposing one or more ground bars for diverting harmful currents away from the sensitive electronic circuit elements. The ground bars are each associated with a row of contact portions of the electronic circuit. Microgaps between each contact portion and the corresponding ground bar are designed to provide an electrical conduit from the contact portion to the ground bar when normal operating voltages are exceeded, thereby channeling excess current harmlessly to ground. Under normal operating conditions, however, the microgaps act as electrical barriers, insulating the contact portions from ground. The microgaps may be filled with any combination of air, vacuum, or known variable voltage material.

公开(公告)号：US20030020590A1

公开(公告)日：2003-01-30

申请号：US09500622

申请日：2000-02-09

Inventor： Stephen J. Whitney ,  Louis Rector ,  Hugh M. Hyatt ,  Anthony D. Minervini ,  Honorio S. Luciano

IPC: H01C007/10

CPC classification number: H05K1/0257 ,  H01C1/14 ,  H01C7/10 ,  H01L2224/48091 ,  H01L2924/07811 ,  H05K1/0259 ,  H05K1/167 ,  H05K2201/0738 ,  H05K2201/10189 ,  H05K2201/10689 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An arrangement of voltage variable materials for the protection of electrical components from electrical overstress (EOS) transients. A device having a plurality of electrical leads, a ground plane and a layer of voltage variable material. The voltage variable material physically bonds the plurality of electrical leads to one another as well as provides an electrical connection between the plurality of electrical leads and the ground plane. A die having a circuit integrated therein is attached to the ground plane. Conductive members electrically connect the plurality of electrical leads to the integrated circuit. At normal operating voltages, the voltage variable material has a high resistance, thus channeling current from the electrical leads to the integrated circuit via the conductive members. In response to a high voltage EOS transient, the voltage variable material essentially instantaneously switches to a low resistance state, channeling the potentially harmful EOS transient to the ground plane and away from the integrated circuit.