公开(公告)号：US08421215B2

公开(公告)日：2013-04-16

申请号：US13331253

申请日：2011-12-20

Applicant: Makoto Tani ,  Takami Hirai ,  Shinsuke Yano ,  Daishi Tanabe

Inventor： Makoto Tani ,  Takami Hirai ,  Shinsuke Yano ,  Daishi Tanabe

IPC: H01L23/12 ,  H01L23/053 ,  H01L23/00 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H05K1/00

CPC classification number: H05K3/4629 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5283 ,  H01L2924/0002 ,  H05K1/0242 ,  H05K3/4623 ,  H05K2201/09227 ,  H05K2201/09236 ,  H05K2201/098 ,  H05K2201/09827 ,  H01L2924/00

Abstract: In the laminated and sintered ceramic circuit board according to the present invention, at least a portion of the inplane conductor is fine-lined, such that the shape of the cross-section surface of the fine-lined inplane conductor is trapezoid, and the height (a), the length (c) of the lower base and the length (d) of the upper base of the trapezoidal cross-section surfaces, and the interval (b) between the lower bases of the trapezoidal cross-section surfaces of the inplane conductors adjacent in a plane parallel to the principal surfaces of the board meet a certain relation. This provides a laminated ceramic circuit board with low open failure rate, short-circuit failure rate and high reliability against high temperature and high humidity in a downsized and short-in-height (thin) semiconductor package.

Abstract translation: 在根据本发明的层压和烧结陶瓷电路板中，面内导体的至少一部分被精细地排列，使得细衬面内导体的横截面的形状是梯形，并且高度 （a）中，梯形截面的下基部的长度（c）和上基部的长度（d）以及梯形截面的梯形截面的下基座之间的间隔（b） 在与板的主表面平行的平面中相邻的面内导体满足一定关系。 这提供了在小型化和短路（薄）半导体封装中具有低开路故障率，短路故障率和高温和高湿度的高可靠性的层压陶瓷电路板。

公开(公告)号：US08418357B2

公开(公告)日：2013-04-16

申请号：US12329614

申请日：2008-12-07

Applicant: Yung-Chieh Chen ,  Cheng-Shien Li ,  Shou-Kuo Hsu

Inventor： Yung-Chieh Chen ,  Cheng-Shien Li ,  Shou-Kuo Hsu

IPC: H05K3/30 ,  H01R43/00

CPC classification number: H05K1/0295 ,  H05K1/0231 ,  H05K1/0237 ,  H05K1/0243 ,  H05K1/113 ,  H05K2201/09236 ,  H05K2201/09954 ,  H05K2201/10545 ,  H05K2201/10636 ,  H05K2201/10689 ,  Y02P70/611 ,  Y10T29/49117 ,  Y10T29/4913

Abstract: A printed circuit board layout method includes the following steps. Providing a printed circuit board with a first layout layer and a second layout layer. Disposing a pair of first conducting portions on the first layout layer to electrically couple to a control chip. Sequentially disposing a pair of second conducting portions, a pair of third conducting portions, and a pair of fourth conducting portions on the second layout layer. Providing a pair of connecting portions to connect the first conducting portions and the third conducting portions. Electrically connecting an electronic device to the second conducting portions, and providing a first and second components are coupled with the third and fourth conducting portions, or electrically coupling the electronic device to the fourth conducting portions, and providing the first and the second components are coupled with the second and third conducting portions.

Abstract translation: 印刷电路板布局方法包括以下步骤。 提供具有第一布局层和第二布局层的印刷电路板。 在第一布局层上布置一对第一导电部分以电耦合到控制芯片。 在第二布局层上顺序地布置一对第二导电部分，一对第三导电部分和一对第四导电部分。 提供一对连接部分以连接第一导电部分和第三导电部分。 将电子设备电连接到第二导电部分，以及提供第一和第二部件与第三和第四导电部分耦合，或将电子器件电耦合到第四导电部分，并且提供第一和第二部件耦合 具有第二和第三导电部分。

公开(公告)号：US08416029B2

公开(公告)日：2013-04-09

申请号：US12671304

申请日：2008-08-01

Applicant: Toshiyuki Kawaguchi ,  Kazutoki Tahara ,  Tsutomu Saga

Inventor： Toshiyuki Kawaguchi ,  Kazutoki Tahara ,  Tsutomu Saga

IPC: H04B3/28 ,  H01P3/08

CPC classification number: H01P3/08 ,  H05K1/0234 ,  H05K1/167 ,  H05K2201/09236 ,  H05K2201/09318 ,  H05K2201/09336 ,  H05K2201/09672

Abstract: The invention provides a transmission noise suppressing structure and a wiring board capable of suppressing a transmission noise transferred through a power supply line, stabilizing a power supply voltage, and reducing signal transmission line cross talk transmitted through the power supply line or a ground layer without being affected by a resistive layer. A transmission noise suppressing structure includes a power supply line and a signal transmission line arranged apart from each other on the same surface; a ground layer arranged apart from the power supply line and the signal transmission line; and a resistive layer arranged apart from the power supply line and the ground layer. The resistive layer has an area (I) which faces the power supply line and an area (II) which does not face the power supply line. The resistive layer and the signal transmission line are apart from each other.

Abstract translation: 本发明提供一种传输噪声抑制结构和布线板，其能够抑制通过电源线传输的传输噪声，稳定电源电压，以及减少通过电源线或接地层传输的信号传输线串扰，而不会 受电阻层影响。 传输噪声抑制结构包括在同一表面上彼此分开布置的电源线和信号传输线; 与电源线和信号传输线分开设置的接地层; 以及与电源线和接地层分开布置的电阻层。 电阻层具有面向电源线的区域（I）和不面向电源线的区域（II）。 电阻层和信号传输线彼此分开。

公开(公告)号：US08403709B2

公开(公告)日：2013-03-26

申请号：US13222854

申请日：2011-08-31

Applicant: Bernard Harold Hammond, Jr. ,  David Patrick Murray ,  Ian Robert George

Inventor： Bernard Harold Hammond, Jr. ,  David Patrick Murray ,  Ian Robert George

IPC: H01R24/00

CPC classification number: H01R13/6466 ,  H01R4/2416 ,  H01R13/6658 ,  H01R13/719 ,  H01R24/64 ,  H01R2107/00 ,  H05K1/0228 ,  H05K1/162 ,  H05K3/4644 ,  H05K2201/09236 ,  H05K2201/09245 ,  H05K2201/09263 ,  H05K2201/10189 ,  Y10S439/941 ,  Y10T29/49117 ,  Y10T29/49204 ,  Y10T29/49222

Abstract: The present disclosure relates to a telecommunications jack including a housing having a port for receiving a plug. The jack also includes a plurality of contact springs adapted to make electrical contact with the plug when the plug is inserted into the port of the housing, and a plurality of wire termination contacts for terminating wires to the jack. The jack further includes a circuit board that electrically connects the contact springs to the wire termination contacts. The circuit board includes a multi-zone crosstalk compensation arrangement for reducing crosstalk at the jack.

公开(公告)号：US20130026636A1

公开(公告)日：2013-01-31

申请号：US13237259

申请日：2011-09-20

Applicant: Makoto TANI ,  Takami HIRAI ,  Shinsuke YANO ,  Tsutomu NANATAKI

Inventor： Makoto TANI ,  Takami HIRAI ,  Shinsuke YANO ,  Tsutomu NANATAKI

IPC: H01L23/498 ,  H05K1/09 ,  H05K1/00

CPC classification number: H01L23/49822 ,  H01L23/15 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K3/4629 ,  H05K2201/0191 ,  H05K2201/068 ,  H05K2201/09227 ,  H05K2201/09236 ,  H05K2201/09672 ,  H01L2924/00

Abstract: A circuit board that can decrease thermal stress acting between a semiconductor element and a board in association with temperature alteration and has high mechanical strength (rigidity) as a whole board (including a multilayer wiring layer) is provided. Ceramic base material having a coefficient of thermal expansion close to that of a semiconductor element and inner layer wiring are integrally sintered, and the circuit board is configured so that fine-lined conductor structure corresponding to a multilayer wiring layer in the inner layer wiring has predetermined width, intralayer interval and interlayer interval. Thereby, thermal stress acting between a semiconductor element and the board when the board is exposed to temperature alteration in a condition where it is joined with the semiconductor element is suppressed, rigidity of the board is maintained, and its reliability against temperature cycle is increased.

Abstract translation: 提供了可以降低与温度变化相关联地在半导体元件和板之间作用的热应力并且具有作为整个板（包括多层布线层）的高机械强度（刚性）的电路板。 具有与半导体元件和内层布线接近的热膨胀系数的陶瓷基材一体烧结，并且电路板被构造成使得与内层布线中的多层布线层相对应的细线导体结构具有预定的 宽度，内膜间隔和层间间隔。 因此，抑制了在与半导体元件接合的状态下板暴露于温度变化时半导体元件与基板之间的热应力，保持板的刚性，并且提高其对温度循环的可靠性。

公开(公告)号：US20120325550A1

公开(公告)日：2012-12-27

申请号：US13530502

申请日：2012-06-22

Applicant: Katsuhiko HAYASHI

Inventor： Katsuhiko HAYASHI

IPC: H01B11/00

CPC classification number: H05K1/0219 ,  H05K1/0228 ,  H05K1/147 ,  H05K9/0064 ,  H05K2201/09236

Abstract: When a GND electrode of a main board is connected to a GND electrode of a daughter board by a flat cable, an end portion of one side of a first GND line is connected to the GND electrode of the main board and an end portion of the other side of the first GND line is connected to the GND electrode of the daughter board. An end portion of one side of a second GND line is insulated from a circuit of the main board and an end portion of the other side of the second GND line is connected to the GND electrode of the daughter board.

Abstract translation: 当主板的GND电极通过扁平电缆连接到子板的GND电极时，第一GND线的一侧的端部连接到主板的GND电极和 第一GND线的另一侧连接到子板的GND电极。 第二GND线的一侧的端部与主板的电路绝缘，并且第二GND线的另一侧的端部连接到子板的GND电极。

公开(公告)号：US08304662B2

公开(公告)日：2012-11-06

申请号：US11806680

申请日：2007-06-01

Applicant: Akiyoshi Saitou ,  Takeshi Midorikawa ,  Toru Kuraishi ,  Chikayuki Kumagai ,  Masashi Fujimoto ,  Kenichiro Abe

Inventor： Akiyoshi Saitou ,  Takeshi Midorikawa ,  Toru Kuraishi ,  Chikayuki Kumagai ,  Masashi Fujimoto ,  Kenichiro Abe

IPC: H05K1/16

CPC classification number: H05K1/0224 ,  H01L2924/0002 ,  H05K1/025 ,  H05K1/0253 ,  H05K1/116 ,  H05K3/4069 ,  H05K3/4602 ,  H05K3/4614 ,  H05K3/4661 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09336 ,  H05K2201/0959 ,  H05K2201/09636 ,  H05K2201/09718 ,  H05K2203/0425 ,  H05K2203/063 ,  Y10T29/49117 ,  H01L2924/00

Abstract: A buildup board includes a buildup layer having a multilayer structure and/or a core layer having a multilayer structure. The multilayer structure includes a signal wiring pattern, a pad connected to the signal wiring pattern, an insulating part arranged around the pad on the same layer as the pad, and a conductor arranged around the insulating part on the same layer as the pad. The multilayer structure has at least two different keepouts where the keepout is defined as a minimum interval between an outline of the pad and the conductor closest to the pad on the same layer.

Abstract translation: 堆积板包括具有多层结构的堆积层和/或具有多层结构的芯层。 多层结构包括信号布线图案，连接到信号布线图案的焊盘，与焊盘相同的层上布置在焊盘周围的绝缘部分，以及布置在与焊盘相同的层上的绝缘部分周围的导体。 所述多层结构具有至少两个不同的保持部，其中所述挡板被定义为所述焊盘的轮廓与最靠近所述焊盘在同一层上的导体之间的最小间隔。

公开(公告)号：US20120228006A1

公开(公告)日：2012-09-13

申请号：US13408062

申请日：2012-02-29

Applicant: Nan-Jang CHEN

Inventor： Nan-Jang CHEN

IPC: H05K1/02

CPC classification number: H05K1/0219 ,  H01P3/08 ,  H05K1/0224 ,  H05K1/0298 ,  H05K2201/0715 ,  H05K2201/09236

Abstract: A printed circuit board (PCB) is disclosed. The PCB includes a substrate have a top surface and a bottom surface. A first conductive layer is disposed on the top surface of the substrate. The first conductive layer comprises a first signal net and a second signal net. An outermost insulating layer is disposed on the top surface of the substrate to cover the substrate and the first conductive layer. The outmost insulating layer comprises an opening to expose a portion of the second signal net. And, a second conductive layer is disposed on the outermost insulating layer and substantially covering at least a portion of the first signal net. The second conductive layer is filled into the opening to electrically connect to the second signal net which is able to provide one of a ground potential and a power potential.

Abstract translation: 公开了印刷电路板（PCB）。 PCB包括具有顶表面和底表面的基底。 第一导电层设置在基板的顶表面上。 第一导电层包括第一信号网和第二信号网。 最外层绝缘层设置在基板的顶表面上以覆盖基板和第一导电层。 最外层绝缘层包括用于暴露第二信号网的一部分的开口。 并且，第二导电层设置在最外绝缘层上并基本上覆盖第一信号网的至少一部分。 将第二导电层填充到开口中以电连接到能够提供地电位和功率电位之一的第二信号网。

公开(公告)号：US20120200372A1

公开(公告)日：2012-08-09

申请号：US13444510

申请日：2012-04-11

Applicant: Robert Ziegler

Inventor： Robert Ziegler

IPC: H03H7/00

CPC classification number: H05K1/162 ,  H03H7/0115 ,  H03H7/42 ,  H03H7/425 ,  H03H2001/0085 ,  H05K2201/09236 ,  H05K2201/09672 ,  H05K2201/1006

Abstract: An electrical circuit arrangement provides a substrate and at least two conductive surfaces. The substrate comprises at least one layer disposed between the conductive surfaces. The conductive surfaces form a capacitor and overlap in part and form an overlapping area. In the event of a displacement of the conductive surfaces relative to one another, the resulting overlapping area is largely constant up to a threshold value of the displacement.

Abstract translation: 电路装置提供衬底和至少两个导电表面。 衬底包括设置在导电表面之间的至少一层。 导电表面形成电容器并且部分重叠并形成重叠区域。 在导电表面相对于彼此移位的情况下，所产生的重叠区域大部分恒定直到位移的阈值。

公开(公告)号：US08237055B2

公开(公告)日：2012-08-07

申请号：US12564734

申请日：2009-09-22

Applicant: Wang-Jia Chen ,  Wei Zhou ,  Yu-Hsu Lin ,  Feng Zhang

Inventor： Wang-Jia Chen ,  Wei Zhou ,  Yu-Hsu Lin ,  Feng Zhang

IPC: H05K1/00

CPC classification number: H05K1/025 ,  H05K1/0245 ,  H05K2201/09236 ,  H05K2201/09318 ,  H05K2201/09345 ,  H05K2201/09727

Abstract: A circuit board includes an insulation layer, a signal layer disposed on one side of the insulation layer, and a ground plane and a power plane disposed on the insulation layer at a side opposite to the signal layer. The insulation layer forms a separating area arranged between the ground plane and the power plane. At least two signal traces parallel to each other are arranged on the signal layer at one side corresponding to one of the ground plane and the power plane. A width of the signal trace close to the separating area is wider than that of the signal trace away from the separating area.

Abstract translation: 电路板包括绝缘层，设置在绝缘层的一侧的信号层，以及设置在与信号层相对的一侧的绝缘层上的接地面和电源面。 绝缘层形成布置在接地平面和电源平面之间的分离区域。 彼此平行的至少两条信号迹线在对应于接地平面和电源平面之一的一侧上布置在信号层上。 靠近分离区域的信号迹线的宽度比远离分离区域的信号迹线宽。