公开(公告)号：US10439624B2

公开(公告)日：2019-10-08

申请号：US15545200

申请日：2016-01-22

Applicant: Circuit Seed, LLC

Inventor： Susan Marya Schober ,  Robert C. Schober ,  Herbert M Shapiro

IPC: H03L7/099 ,  H03L7/24 ,  H03K3/03 ,  H03B5/12 ,  H03K3/354 ,  H03L7/04 ,  H03L7/089 ,  H03L7/091

Abstract: A novel phase locked loop design utilizing novel phase-frequency detector, charge pump, loop filter and voltage controlled oscillator is disclosed. The phase-frequency detector includes a dual reset D-flip flop for use in multi-GHz phase locked loops. Traditional dead zone issues associated with phase frequency detector are improved/addressed by use with a charge transfer-based PLL charge pump.

公开(公告)号：US20190305783A1

公开(公告)日：2019-10-03

申请号：US15944567

申请日：2018-04-03

Applicant: Silicon Laboratories Inc.

Inventor： Aaron J. Caffee ,  Russell Croman ,  Brian G. Drost

IPC: H03L7/093 ,  H04L7/033 ,  H03L7/087 ,  H03L7/091 ,  H05K1/02

Abstract: A clock generator includes an oscillator configured to generate an oscillating signal and a signal path configured to provide an output clock signal based on the oscillating signal. In response to a control signal, the clock generator is configured to neutralize periodic phase perturbations in the oscillating signal using opposing periodic phase perturbations. The neutralization may occur in the signal path. The signal path may be responsive to the control signal to adjust at least one of a duty cycle, a rise time, and a fall time of the output clock signal to cause alternating phase perturbations of the periodic phase perturbations to apply as the opposing periodic phase perturbations in the output clock signal. The neutralization may occur in the oscillator. The clock generator may include an auxiliary path configured to provide an auxiliary signal to the oscillator.

公开(公告)号：US20190243410A1

公开(公告)日：2019-08-08

申请号：US16389340

申请日：2019-04-19

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Toshitada SAITO ,  Akihisa FUJIMOTO

IPC: G06F1/06 ,  H03L7/099 ,  H03L7/08 ,  H03L7/07 ,  H03L7/091 ,  H04L7/033 ,  H04L7/00 ,  G06F13/42

CPC classification number: G06F1/06 ,  G06F1/12 ,  G06F13/38 ,  G06F13/4282 ,  H03L7/00 ,  H03L7/07 ,  H03L7/0807 ,  H03L7/091 ,  H03L7/099 ,  H04L7/0004 ,  H04L7/0012 ,  H04L7/033 ,  H04L25/085 ,  H04L25/14

Abstract: According to one embodiment, an interface system includes a receiver, a first clock generator, a second clock generator, and a sampling circuit. The receiver is configured to receive a first clock and serial data from a host. The first clock generator includes a first voltage controlled oscillator (VCO) and is configured to generate a second clock on the basis of the first clock. The second clock generator includes a second voltage controlled oscillator (VCO) and is configured to generate a third clock on the basis of the serial data. The sampling circuit is configured to sample reception data on the basis of the third clock and the serial data.

公开(公告)号：US20190238142A1

公开(公告)日：2019-08-01

申请号：US16242475

申请日：2019-01-08

Applicant: Rambus Inc.

Inventor： Jared L. ZERBE ,  Brian S. LEIBOWITZ ,  Hsuan-Jung SU ,  John Cronan EBLE, III ,  Barry William DALY ,  Lei LUO ,  Teva J. STONE ,  John WILSON ,  Jihong REN ,  Wayne D. DETTLOFF

IPC: H03L7/091 ,  H03L7/099 ,  H03L7/08 ,  G11C7/10 ,  H03L7/00 ,  H04L7/00 ,  H03K5/156 ,  H04L7/033 ,  G11C7/22

CPC classification number: H03L7/091 ,  G11C7/04 ,  G11C7/1066 ,  G11C7/1093 ,  G11C7/222 ,  H03K5/1565 ,  H03L7/00 ,  H03L7/0802 ,  H03L7/099 ,  H04L7/0008 ,  H04L7/0037 ,  H04L7/0079 ,  H04L7/0087 ,  H04L7/033

Abstract: A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.

公开(公告)号：US10367634B1

公开(公告)日：2019-07-30

申请号：US16137500

申请日：2018-09-20

Applicant: GLOBAL UNICHIP CORPORATION ,  TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Po-Shing Yu

IPC: H04L25/03 ,  H04L7/00 ,  H03L7/08 ,  H03L7/091

Abstract: A clock and data recovery device includes a data analysis circuitry, a loop filter circuitry, a phase rotator circuitry, a multiplexer circuitry, and a phase interpolator circuitry. The data analysis circuitry analyzes input data according to a first clock signal and a second clock signal to generate an error signal. The loop filter circuitry updates an adjustment signal according to the error signal. The phase rotator circuitry adjusts rotation signals according to the adjustment signal and limit values if the adjustment signal is updated. The multiplexer circuitry outputs one of the rotation signals as a phase control signal according to third clock signals. The phase interpolator circuitry adjusts the first and the second clock signals according to the phase control signal and fourth clock signals.

公开(公告)号：US20190214976A1

公开(公告)日：2019-07-11

申请号：US16019070

申请日：2018-06-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wanghua Wu ,  Chih-Wei Yao

IPC: H03K5/156 ,  H03L7/099 ,  H03L7/091 ,  H04L25/49 ,  H03L7/08 ,  H03L7/097

Abstract: A system and method for fast converging reference clock duty cycle correction for a digital to time converter (DTC) based analog fractional-N phase-locked loop (PLL) are herein disclosed. According to one embodiment, an electronic circuit includes a clock doubler, a comparator that outputs a value representing a difference between a voltage at a voltage-to-current (Gm) circuit and a reference voltage that is adjusted to compensate for an offset of the comparator, and a duty cycle calibration circuit that receives the value output from the comparator and adjusts a duty cycle of the PLL by extracting an error from the value output from the comparator and delaying a clock edge of the duty cycle according to the extracted error.

公开(公告)号：US10348315B2

公开(公告)日：2019-07-09

申请号：US15795119

申请日：2017-10-26

Applicant: Perceptia Devices, Inc.

Inventor： André Grouwstra ,  Julian Jenkins

IPC: H03L7/14 ,  H03L7/197 ,  H03L7/091 ,  H03L7/087 ,  H03L7/08 ,  H03L7/085 ,  H03L7/093 ,  H03L7/099 ,  H03L7/181 ,  H03L7/23

Abstract: A phase-locked loop (PLL) has an oscillator, a counter and a register to sample the oscillator phase as an integer number. A phase predictor uses a fractional-N frequency control word (FCW) to calculate a predicted phase as an integer number. The integer difference between the sampled phase and the predicted phase is used as loop filter input, to generate an oscillator control signal that adjusts the oscillator frequency. The phase predictor may provide noise shaping, for example via a MASH modulator. A first sleep mode control signal blocks a reference clock and feedback of the oscillator clock to the counter. It may also freeze loop filter parameters and block the output clock. A second sleep mode control signal may stop the oscillator.

公开(公告)号：US10340923B2

公开(公告)日：2019-07-02

申请号：US15354066

申请日：2016-11-17

Applicant: Intel Corporation

Inventor： Cho-Ying Lu ,  William Yee Li ,  Khoa Minh Nguyen ,  Ashoke Ravi ,  Maneesha Yellepeddi ,  Binta M. Patel

IPC: H03L7/085 ,  H03L1/00 ,  H03L7/099 ,  H03L7/08 ,  H03L7/091

Abstract: A system for assigning a characterization and calibrating a parameter is disclosed. The system includes a frequency measurement circuit and a finite state machine. The frequency measurement circuit is configured to measure frequencies of an oscillatory signal and to generate a measurement signal including measured frequencies. The finite state machine is configured to control measurements by the frequency measurement circuit, to assign a characterization to a parameter based on the measurement signal, and to generate a calibration signal based on the characterized parameter.

公开(公告)号：US10305499B2

公开(公告)日：2019-05-28

申请号：US15349220

申请日：2016-11-11

Applicant: Seiko Epson Corporation

Inventor： Masayoshi Todorokihara ,  Aritsugu Yajima ,  Tetsuro Matsumoto

IPC: H03B21/00 ,  H03L7/093 ,  H03K19/21 ,  H03L7/091 ,  H03L7/085 ,  H03L7/16

Abstract: A frequency synthesizer includes: an oscillating section that generates a first signal; a frequency ratio measuring section that measures a frequency ratio of the first signal and a second signal by using the first signal and the second signal; a comparing section that compares the frequency ratio, which is measured by the frequency measuring section, with a target value of a frequency ratio; and a filter that is disposed on a preceding stage of the comparing section. A frequency of the first signal of the oscillating section is adjusted on the basis of a comparison result of the comparing section.

公开(公告)号：US10298243B2

公开(公告)日：2019-05-21

申请号：US15575830

申请日：2016-06-08

Applicant: Intel IP Corporation

Inventor： Thomas Mayer

IPC: H03L7/06 ,  H03L7/099 ,  H03L7/197 ,  H03L7/091 ,  H04B1/02

Abstract: A system for determining a correction for an output value of a time-to-digital converter within a phase-locked loop is provided. The output value relates to a time difference between an input signal and a reference signal supplied to the time-to-digital converter. The system includes a digitally-controlled oscillator configured to generate a first signal independently from the output signal. The first signal has a first frequency different from an integer multiple of a reference frequency of the reference signal. The system further includes a frequency divider configured to generate the input signal for the time-to-digital converter based on the first signal. The input signal has a second frequency being a fraction of the first frequency. Further, the system includes a processing unit configured to calculate the correction using a distribution of output values of multiple time differences.