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公开(公告)号：US09819344B2
公开(公告)日：2017-11-14
申请号：US14015028
申请日：2013-08-30
Applicant: STMicroelectronics International N.V.
Inventor： Tanmoy Sen , Aswani Aditya Kumar Tadinada
IPC: H03K17/94 , H03K19/003
CPC classification number: H03K19/00369 , Y10T307/747
Abstract: An apparatus comprising: a sensor; and a resistor array comprising a set of resistors; wherein on a first cycle: at least one first of said resistors is configured to provide a first resistance value; and on a second cycle: at least one second of said resistors is configured to provide said first resistance value.
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公开(公告)号：US09819268B2
公开(公告)日：2017-11-14
申请号：US15016908
申请日：2016-02-05
Applicant: STMicroelectronics International N.V.
Inventor： Matthieu Thomas , Bohumil Janik , Ondrej Tlaskal
CPC classification number: H02M3/158 , H02M3/1588 , H02M2001/0009 , H02M2001/0025 , H02M2001/0032 , Y02B70/1466 , Y02B70/16
Abstract: An electronic device includes first and second transistors coupled in series between first and second source voltage levels. An inductor is coupled between a node coupling the first and second transistors and a load. Control logic is operative to generate control pulses operative to switch the first and second transistors. The controller generates the control pulses as a continuous stream of control pulses in a continuous conduction mode, and skips generation of some control pulses in a discontinuous conduction mode in response to a pulse skipping signal. A pulse skipping circuit is operative to generate a sense voltage as a function of an inductor current in the inductor, compare the sense voltage to ground, and generate a pulse skipping signal to the control logic when the sense voltage is below ground.
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公开(公告)号：US09812219B2
公开(公告)日：2017-11-07
申请号：US14640601
申请日：2015-03-06
Applicant: STMicroelectronics International N.V.
Inventor： Nishu Kohli
IPC: G11C29/10 , G11C29/24 , G11C29/00 , G11C29/14 , G11C29/54 , G11C29/52 , G11C29/50 , G11C29/56 , G11C11/34 , G11C11/22 , G01R31/3183 , G11C11/4063
CPC classification number: G11C29/10 , G01R31/318307 , G01R31/318342 , G01R31/318371 , G11C11/2273 , G11C11/2275 , G11C11/34 , G11C11/4063 , G11C29/00 , G11C29/14 , G11C29/24 , G11C29/50 , G11C29/52 , G11C29/54 , G11C29/56004 , G11C29/56008
Abstract: An embodiment of a method for automated test pattern generation (ATPG), a system for ATPG, and a memory configured for ATPG. For example, an embodiment of a memory includes a first test memory cell, a data-storage memory cell, and a test circuit configured to enable the test cell and to disable the data-storage cell during a test mode.
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公开(公告)号：US09804225B2
公开(公告)日：2017-10-31
申请号：US14472220
申请日：2014-08-28
Applicant: STMicroelectronics International N.V.
Inventor： Saurabh Kumar Singh , Balwant Singh
IPC: G01R31/28 , G01R31/317
CPC classification number: G01R31/31725
Abstract: A test circuit measures both the rising edge delay and the falling edge delay associated with a logic cell. The test circuit includes a flip-flop type ring oscillator with two groups of logic cells connected in series in the oscillation path. A first multiplexor switches the ring oscillator between a rising edge and a falling edge mode. A second multiplexer causes the second group of logic cells to be included or excluded from the oscillation path. By measuring the oscillation period in the various modes, the rising edge and falling edge delays can be individually calculated.
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公开(公告)号：US09794054B2
公开(公告)日：2017-10-17
申请号：US14788721
申请日：2015-06-30
Applicant: STMicroelectronics International N.V.
Inventor： Tapas Nandy , Nitin Gupta
CPC classification number: H04L7/0008 , G06F1/10 , H04J3/0685 , H04L1/0026 , H04L5/00 , H04L7/02 , H04L7/027 , H04L7/033 , H04L7/0337
Abstract: A source synchronous data transmission system includes a data transmitting device and a data receiving device. A dedicated data line carries a data signal from the data transmission device to the data receiving device. A dedicated clock line carries a modulated clock signal from the data transmission device to the data receiving device. The data transmission device includes a clock data driver configured to encode data into the modulated clock signal by modulating an amplitude of the modulated clock signal. Thus, the clock line of the source synchronous data transmission system carries the clock signal and additional data.
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Patent Agency Ranking
公开(公告)号：US09753279B2
公开(公告)日：2017-09-05
申请号：US14564237
申请日：2014-12-09
Inventor： Benedetto Vigna , Marco Ferrera , Sonia Costantini , Marco Salina
CPC classification number: G02B26/0841 , B81B3/0045 , B81B2201/042 , B81B2203/0154 , B81C1/00198 , G02B27/1006 , H02N1/002 , H02N1/006 , H04N9/3129 , H04N9/3135 , Y10T29/49002
Abstract: An electrostatically actuated oscillating structure includes a first stator subregion, a second stator subregion, a first rotor subregion and a second rotor subregion. Torsional elastic elements mounted to the first and second rotor subregions define an axis of rotation. A mobile element is coupled to the torsional elastic elements. The stator subregions are electrostatically coupled to respective regions of actuation on the mobile element. The stator subregions exhibit an element of structural asymmetry such that the electrostatic coupling surface between the first stator subregion and the first actuation region differs from the electrostatic coupling surface between the second stator subregion and the second actuation region.
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公开(公告)号：US09747477B2
公开(公告)日：2017-08-29
申请号：US14810354
申请日：2015-07-27
Applicant: STMicroelectronics International N.V.
Inventor： Giuliano Manzi
CPC classification number: G06K7/10237 , G06K7/0008 , G06K19/0723
Abstract: In one embodiment a UHF RFID reader is adapted to operate in either a reader mode or in a tag emulation mode, wherein in the reader mode the UHF RFID reader communicates with at least one RFID tag to access the at least one tag's memory contents and in the tag emulation mode the UHF RFID reader communicates with at least one other UHF RFID reader to share memory content with the at least one other UHF RFID reader. Furthermore, an RFID network and a method for communication in an RFID network are described.
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公开(公告)号：US09746861B2
公开(公告)日：2017-08-29
申请号：US14275573
申请日：2014-05-12
Applicant: STMicroelectronics International N.V.
Inventor： Laurent Perier
CPC classification number: G05F1/46 , H02J1/00 , Y10T307/406
Abstract: A stand-alone DC power network is provided with a DC to DC power converter only, and does not have a converter that will convert AC to DC. In addition, each of the different terminals that provides the DC voltage at different levels will be ranked according to priority as to which ones are the most important to supply the full voltage to, and which ones are of secondary importance in the event there is insufficient power in the system to provide full voltage at the specified current for the different loads. A processor monitors the voltage and current at each of the terminals, and in the event a current is attempted to be drawn from the system which would cause a first priority terminal to be reduced in voltage, the processor will instead reduce the power provided to the second priority terminal and ensure that the first priority terminal does not have a significant reduction in the specified voltage or the amount of current supplied to that terminal at the specified voltage.
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公开(公告)号：US09722623B1
公开(公告)日：2017-08-01
申请号：US15382813
申请日：2016-12-19
Applicant: STMicroelectronics International N.V.
Inventor： Ashish Kumar , Chandrajit Debnath
CPC classification number: H03M1/0665 , H03M3/464
Abstract: An embodiment ADC device includes a plurality of comparator elements, each comparator element of the plurality of comparator elements having a first input connected to an input port, each comparator element of the plurality of comparator elements having a second input port connected to a reference signal port. The ADC device further has a switch matrix having routing circuitry connected to an output of each comparator of the plurality of comparators, and a plurality of latches, with each latch of the plurality of latches having an input connected to the routing circuitry. The routing circuitry is configured to connect the output of each comparator of the plurality of comparators to an input of each latch of the plurality of latches according to one or more signals received at one or more control ports.
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公开(公告)号：US09705665B2
公开(公告)日：2017-07-11
申请号：US15009696
申请日：2016-01-28
Applicant: STMicroelectronics International N.V.
Inventor： Abhishek Chowdhary , Vivek Uppal , Alok Kaushik , Sajal Kumar Mandal , Tapas Nandy , Sanjeev Chopra
CPC classification number: H04L7/0087 , H03L7/0807 , H03L7/091 , H04L7/0004 , H04L7/005 , H04L7/033 , H04L7/0331 , H04L7/0338 , H04L25/03057 , H04L43/022
Abstract: A method, algorithm, architecture, circuit and/or system that compensates for frequency difference in oversampled CDRs. The oversampled CDR uses a programmable divider whose division ratio is changed, for one or more cycles, from its usual division ratio, when accumulated phase movement in either direction exceeds a threshold. Accordingly, the elasticity buffer in oversampled CDRs can be made much smaller or entirely eliminated, resulting in less area, and reduced or eliminated dependence of max allowed burst size on ppm difference. The threshold can be kept programmable, and more than half unit interval, to provide robustness towards high frequency jitter.
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