公开(公告)号：US08525328B2

公开(公告)日：2013-09-03

申请号：US13182469

申请日：2011-07-14

Applicant: Jiin-Shing Perng ,  Min-Lin Lee ,  Shinn-Juh Lai ,  Huey-Ru Chang

Inventor： Jiin-Shing Perng ,  Min-Lin Lee ,  Shinn-Juh Lai ,  Huey-Ru Chang

IPC: H01L23/34

CPC classification number: H01L25/165 ,  H01L23/3107 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00

Abstract: The disclosure relates to a power device package structure. By employing the metal substrate of the power device package structure serve as a bottom electrode of a capacitor, the capacitor is integrated into the power device package structure. A dielectric material layer and a upper metal layer sequentially disposed on the metal substrate.

Abstract translation: 本公开涉及功率器件封装结构。 通过采用功率器件封装结构的金属衬底作为电容器的底部电极，将电容器集成到功率器件封装结构中。 依次设置在金属基板上的电介质材料层和上金属层。

公开(公告)号：US20120168217A1

公开(公告)日：2012-07-05

申请号：US13197283

申请日：2011-08-03

Applicant: Chien-Min Hsu ,  Min-Lin Lee ,  Cheng-Liang Cheng ,  Li-Duan Tsai

Inventor： Chien-Min Hsu ,  Min-Lin Lee ,  Cheng-Liang Cheng ,  Li-Duan Tsai

IPC: H05K1/16

CPC classification number: H05K1/0231 ,  H01G9/012 ,  H01G9/15 ,  H01L23/49822 ,  H01L23/642 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2924/14 ,  H01L2924/19041 ,  H05K1/162 ,  H05K3/4608 ,  H05K2201/0187 ,  H05K2201/09309 ,  H05K2203/0315

Abstract: An embedded capacitor substrate module includes a substrate, a metal substrate and a solid electrolytic capacitor material. The solid electrolytic capacitor material is formed on the metal substrate, so as to form a solid electrolytic capacitor with the substrate. The embedded capacitor substrate module further includes an electrode lead-out region formed by extending the substrate and the metal substrate. The metal substrate serves as a first electrode, and the substrate serves as a second electrode. An insulating material is formed between the substrate and the metal substrate. Therefore, the embedded capacitor substrate module is not only advantageous in having a large capacitance as the conventional solid capacitor, but also capable of being drilled or plated and electrically connected to other circuits after being embedded in a printed circuit board.

Abstract translation: 嵌入式电容器基板模块包括基板，金属基板和固体电解电容器材料。 在金属基板上形成固体电解电容器材料，以便与基板形成固体电解电容器。 嵌入式电容器基板模块还包括通过使基板和金属基板延伸而形成的电极引出区域。 金属基板用作第一电极，并且基板用作第二电极。 在基板和金属基板之间形成绝缘材料。 因此，嵌入式电容器基板模块不仅有利于具有作为常规固体电容器的大电容，而且还可以在嵌入印刷电路板中之后被钻孔或电镀并电连接到其它电路。

公开(公告)号：US08174840B2

公开(公告)日：2012-05-08

申请号：US12260254

申请日：2008-10-29

Applicant: Uei-Ming Jow ,  Chang-Sheng Chen ,  Chin-Sun Shyu ,  Min-Lin Lee ,  Shinn-Juh Lay ,  Ying-Jiunn Lai

Inventor： Uei-Ming Jow ,  Chang-Sheng Chen ,  Chin-Sun Shyu ,  Min-Lin Lee ,  Shinn-Juh Lay ,  Ying-Jiunn Lai

IPC: H05K1/16

CPC classification number: H01L23/14 ,  H01F17/0006 ,  H01F41/046 ,  H01F2017/0066 ,  H01G4/30 ,  H01G4/40 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49894 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  H05K1/162 ,  H05K1/165 ,  H05K3/4626 ,  H05K3/4652 ,  H05K3/4655 ,  H05K3/4688 ,  H05K2201/0187 ,  H05K2201/086 ,  H05K2201/09672 ,  H01L2924/00

Abstract: A multi-functional composite substrate structure is provided. The first substrate with high dielectric constant and the second substrate with low dielectric constant and low loss tangent are interlaced above the third substrate. One or more permeance blocks may be formed above each substrate, so that one or more inductors may be fabricated thereon. One or more capacitors may be fabricated on the first substrate. Also, one or more signal transmission traces of the system impedance are formed on the second substrate of the outside layer. Therefore, the inductance of the inductor(s) is effectively enhanced. Moreover, the area of built-in components is reduced. Furthermore, it has shorter delay time, smaller dielectric loss, and better return loss for the transmission of high speed and high frequency signal.

Abstract translation: 提供了多功能复合基板结构。 具有高介电常数的第一衬底和具有低介电常数和低损耗角正切的第二衬底交错在第三衬底之上。 一个或多个导磁块可以形成在每个衬底之上，使得可以在其上制造一个或多个电感器。 可以在第一基板上制造一个或多个电容器。 此外，系统阻抗的一个或多个信号传输迹线形成在外层的第二基板上。 因此，有效地提高了电感器的电感。 此外，内置组件的面积减少。 此外，它具有更短的延迟时间，更小的介电损耗和更高的传输高速和高频信号的回波损耗。

公开(公告)号：US07894172B2

公开(公告)日：2011-02-22

申请号：US12191179

申请日：2008-08-13

Applicant: Chi-Liang Pan ,  Min-Lin Lee ,  Shinn-Juh Lai ,  Shih-Hsien Wu ,  Chen-Hsuan Chiu

Inventor： Chi-Liang Pan ,  Min-Lin Lee ,  Shinn-Juh Lai ,  Shih-Hsien Wu ,  Chen-Hsuan Chiu

IPC: H05F3/00

CPC classification number: H01L23/60 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/0257 ,  H05K1/0259 ,  H05K1/0373 ,  H05K1/116 ,  H05K1/167 ,  H05K3/4688 ,  H05K2201/0738 ,  H05K2201/09718 ,  H01L2924/00014

Abstract: An ESD protection structure is provided. A substrate includes a first voltage variable material and has a first surface, a second surface substantially paralleled to the first surface and a via connecting the first and second surfaces. A first metal layer is disposed in the substrate for coupling to a ground terminal. The first voltage variable material is in a conductive state when an ESD event occurs, such that the via is electrically connected with the first metal layer to form a discharge path, and the first voltage variable material is in an isolation state when the ESD event is absent, such that the via is electrically isolated from the first metal layer.

Abstract translation: 提供ESD保护结构。 衬底包括第一电压可变材料，并具有第一表面，与第一表面基本平行的第二表面和连接第一表面和第二表面的通孔。 第一金属层设置在衬底中用于耦合到接地端子。 当ESD事件发生时，第一电压可变材料处于导通状态，使得通孔与第一金属层电连接以形成放电路径，并且当ESD事件为ESD时，第一电压可变材料处于隔离状态 不存在，使得通孔与第一金属层电隔离。

公开(公告)号：US07804678B2

公开(公告)日：2010-09-28

申请号：US11844280

申请日：2007-08-23

Applicant: Shih-Hsien Wu ,  Shinn-Juh Lai ,  Min-Lin Lee ,  Shur-Fen Liu

Inventor： Shih-Hsien Wu ,  Shinn-Juh Lai ,  Min-Lin Lee ,  Shur-Fen Liu

IPC: H01G4/06

CPC classification number: H01G4/06 ,  H01G4/12 ,  H01G4/1227 ,  H01G4/14 ,  H01G4/20 ,  H01G4/206 ,  H05K1/162 ,  H05K3/4611 ,  H05K2201/0187 ,  H05K2201/0195 ,  H05K2201/09672 ,  H05K2201/2036 ,  Y10T29/417

Abstract: A capacitor device with a capacitance is introduced. The capacitor device includes at least one capacitive element. The at least capacitive element comprises a pair of first conductive layers being opposed to each other, at least one first dielectric layer formed on a surface of at least one of the first conductive layers, and a second dielectric layer being sandwiched between the first conductive layers. The first dielectric layer has a first dielectric constant and the second dielectric layer has a second dielectric constant. The capacitance of the capacitor device depends on dielectric parameters of the first dielectric layer and the second dielectric layer. The dielectric parameters comprise the first dielectric constant and thickness of the at least one first dielectric layer and the second dielectric constant and thickness of the second dielectric layer.

公开(公告)号：US07714590B2

公开(公告)日：2010-05-11

申请号：US11708935

申请日：2007-02-20

Applicant: Uei-Ming Jow ,  Min-Lin Lee ,  Shinn-Juh Lay ,  Chin-Sun Shyu ,  Chang-Sheng Chen

Inventor： Uei-Ming Jow ,  Min-Lin Lee ,  Shinn-Juh Lay ,  Chin-Sun Shyu ,  Chang-Sheng Chen

IPC: G01R31/12 ,  G01R31/02 ,  H01G4/30 ,  H01G4/228

CPC classification number: H05K1/0268 ,  G01R31/2818 ,  H05K1/0298 ,  H05K1/116 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167

Abstract: A method is provided for testing a built-in component including multiple terminals in a multi-layered circuit board. At least one signal pad is provided on a top surface of the multi-layered circuit board for signal transmission. Each of the signal pads are electrically connected to one of the multiple terminals. At least one test pad is provided on the top surface of the multi-layered circuit board and each of the test pads is electrically connected to one of the multiple terminals. Then, detection occurs regarding one of the signal pads and one of the test pads that are electrically connected to a same one of the multiple terminals in order to determine a connection status of an electric path extending from the one signal pad through the same one terminal to the one test pad.

Abstract translation: 提供一种用于在多层电路板中测试包括多个端子的内置组件的方法。 在用于信号传输的多层电路板的顶表面上提供至少一个信号焊盘。 每个信号焊盘电连接到多个端子中的一个。 在多层电路板的顶表面上提供至少一个测试焊盘，并且每个测试焊盘电连接到多个端子之一。 然后，对于电连接到多个端子中的一个的一个信号焊盘和测试焊盘之一进行检测，以便确定从一个信号焊盘延伸通过相同的一个端子的电通路的连接状态 到一个测试垫。

公开(公告)号：US20090219668A1

公开(公告)日：2009-09-03

申请号：US12392272

申请日：2009-02-25

Applicant: Chien-Min Hsu ,  Min-Lin Lee ,  Shinn-Juh Lai ,  Huey-Ru Chang ,  Ray-Fong Hong

Inventor： Chien-Min Hsu ,  Min-Lin Lee ,  Shinn-Juh Lai ,  Huey-Ru Chang ,  Ray-Fong Hong

IPC: H01G4/005

CPC classification number: H05K1/162 ,  H01G4/228 ,  H01G4/248 ,  H01G4/33 ,  H01L23/49827 ,  H01L23/50 ,  H01L2224/16225 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/3011 ,  H05K1/112 ,  H05K2201/09309 ,  H05K2201/09663 ,  H05K2201/09736 ,  H05K2201/09845 ,  H05K2201/10674

Abstract: A capacitive device is provided. The capacitive device includes a first electrode and a second electrode below the first electrode and spaced apart from the first electrode, wherein at least one of the first electrode and the second electrode includes a plurality of conductive step sections, the plurality of conductive step sections having different heights. The capacitive device also includes an insulating region between the first electrode and the second electrode; and at least one slot formed on one of the first electrode and the second electrode.

Abstract translation: 提供了一种电容器件。 该电容性装置包括第一电极和第一电极之下并与第一电极间隔开的第二电极，其中第一电极和第二电极中的至少一个包括多个导电步骤部分，所述多个导电步骤部分具有 不同的高度 电容性装置还包括在第一电极和第二电极之间的绝缘区域; 以及形成在第一电极和第二电极之一上的至少一个槽。

公开(公告)号：US20090002916A1

公开(公告)日：2009-01-01

申请号：US11987756

申请日：2007-12-04

Applicant: Chang Lin Wei ,  Chin Sun Shyu ,  Cheng Hua Tsai ,  Min Lin Lee

Inventor： Chang Lin Wei ,  Chin Sun Shyu ,  Cheng Hua Tsai ,  Min Lin Lee

IPC: H01G4/005

CPC classification number: H01G4/005 ,  H01G4/33

Abstract: An interdigital capacitor includes a first finger electrode structure and a second finger electrode structure. The first finger electrode structure has a first electrode and a plurality of first extending electrodes. The first extending electrodes are linearly disposed and arranged. The second finger electrode structure has a second electrode and a plurality of second extending electrodes. The second extending electrodes are linearly disposed and arranged. The second finger electrode structure interlaces with the first finger electrode structure. At least one pair of first coupling electrodes extend respectively from the neighboring first and second extending electrodes and are disposed between them.

Abstract translation: 叉指电容器包括第一指状电极结构和第二指状电极结构。 第一指状电极结构具有第一电极和多个第一延伸电极。 第一延伸电极线性地布置和布置。 第二手指电极结构具有第二电极和多个第二延伸电极。 第二延伸电极线性地布置和布置。 第二指状电极结构与第一指状电极结构交织。 至少一对第一耦合电极分别从相邻的第一和第二延伸电极延伸并设置在它们之间。

公开(公告)号：US07349196B2

公开(公告)日：2008-03-25

申请号：US11156350

申请日：2005-06-17

Applicant: Chih-Hao Chang ,  Shih-Hsien Wu ,  Min-Lin Lee ,  Shinn-Juh Lay

Inventor： Chih-Hao Chang ,  Shih-Hsien Wu ,  Min-Lin Lee ,  Shinn-Juh Lay

IPC: H01G4/06

CPC classification number: H05K1/024 ,  H01L23/49822 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01P3/081 ,  H01P3/085 ,  H05K1/0298 ,  H05K3/386 ,  H05K2201/0187 ,  H05K2201/0195 ,  H05K2201/09881 ,  H01L2924/00

Abstract: A composite distributed dielectric structure includes one or more conductor layers, one or more dielectric layers distributed on the conductor layers, and one or more conductor traces distributed on the dielectric layers. One or more dielectric plates can be further formed around the conductor traces. The dielectric layers or plates may or may not have plural dielectric materials therein. Each conductor trace lies on a dielectric material without crossing two different dielectric materials. Two or more dielectric layers may be stacked on the conductor layers.

Abstract translation: 复合分布介质结构包括一个或多个导体层，分布在导体层上的一个或多个电介质层和分布在电介质层上的一个或多个导体迹线。 可以在导体迹线周围进一步形成一个或多个电介质板。 介电层或板可以具有或可以不具有多个电介质材料。 每个导体迹线位于介电材料上，而不会穿过两种不同的介电材料。 可以在导体层上堆叠两个或更多个电介质层。

公开(公告)号：US07345366B2

公开(公告)日：2008-03-18

申请号：US11131741

申请日：2005-05-18

Applicant: Uei-Ming Jow ,  Min-Lin Lee ,  Shinn-Juh Lay ,  Chin-Sun Shyu ,  Chang-Sheng Chen

Inventor： Uei-Ming Jow ,  Min-Lin Lee ,  Shinn-Juh Lay ,  Chin-Sun Shyu ,  Chang-Sheng Chen

IPC: H01L23/48 ,  H01L23/58 ,  G01R31/26

CPC classification number: H05K1/0268 ,  G01R31/2818 ,  H05K1/0298 ,  H05K1/116 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167

Abstract: A multi-layered circuit board a built-in component including multiple terminals, at least one signal pad formed on a top surface of the multi-layered circuit board for signal transmission, each of the at least one signal pad corresponding to one of the multiple terminals, and at least one test pad formed on the top surface of the multi-layered circuit board, each of the at least one test pad corresponding to one of the at least one signal pad for testing an electric path extending from the one signal pad through the one terminal to the each of the at least one test pad.

Abstract translation: 一种多层电路板，包括多个端子的内置组件，至少一个形成在用于信号传输的多层电路板的顶表面上的信号焊盘，所述至少一个信号焊盘中的每一个对应于多个 端子和形成在多层电路板的顶表面上的至少一个测试焊盘，所述至少一个测试焊盘中的每一个对应于至少一个信号焊盘中的一个，用于测试从一个信号焊盘延伸的电路径 通过所述一个端子到所述至少一个测试垫中的每一个。