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    NAND type dual bit nitride read only memory
    61.
    发明授权
    NAND type dual bit nitride read only memory 有权
    NAND型双位氮化物只读存储器

    公开(公告)号：US06927448B2

    公开(公告)日：2005-08-09

    申请号：US10682861

    申请日：2003-10-14

    申请人： Chien-Hung Liu

    发明人： Chien-Hung Liu

    IPC分类号： H01L21/8246 ,  H01L27/115 ,  H01L29/792 ,  H01L29/788

    CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L29/513 ,  H01L29/518 ,  H01L29/7923

    摘要： A NAND type dual bit nitride read only memory and a method for fabricating thereof are provided. Firstly, a plurality of isolation layers, which are spaced and parallel to each other are formed in the substrate. Next, a plurality of word lines and a plurality of oxide-nitride-oxide (ONO) stack structures are formed on the substrate. The word lines are spaced and parallel to each other, and also the word lines are perpendicular to the isolation layers. Each of the ONO stack structure is located between the corresponding word line and the substrate. And then a plurality of discontinuous bit lines, which are located between the word lines and between the isolation layers are formed on the substrate. The structure of the present invention of the NAND type dual bit nitride read only memory is similar to that of a complementary metal-oxide semiconductor (CMOS), and their fabrication processes are fully compatible.

    摘要翻译： 提供NAND型双位氮化物只读存储器及其制造方法。 首先，在衬底中形成彼此间隔开并平行的多个隔离层。 接下来，在基板上形成多个字线和多个氧化物 - 氮化物 - 氧化物（ONO）堆叠结构。 字线彼此间隔开并平行，字线也垂直于隔离层。 每个ONO堆叠结构位于相应的字线和基板之间。 然后，在基板上形成位于字线之间和隔离层之间的多个不连续位线。 本发明的NAND型双位氮化物只读存储器的结构类似于互补金属氧化物半导体（CMOS）的结构，并且它们的制造工艺是完全兼容的。

    Fabrication method for a silicon nitride read-only memory
    63.
    发明授权
    Fabrication method for a silicon nitride read-only memory 有权

    公开(公告)号：US06613632B2

    公开(公告)日：2003-09-02

    申请号：US10158260

    申请日：2002-05-28

    申请人： Chien-Hung Liu ,  Shyi-Shuh Pan ,  Shou-Wei Huang

    发明人： Chien-Hung Liu ,  Shyi-Shuh Pan ,  Shou-Wei Huang

    IPC分类号： H01L218247

    CPC分类号： H01L27/11568 ,  H01L21/28282 ,  H01L27/115

    摘要： A fabrication method for a read-only memory with a silicon nitride floating gate is provided. A first oxide layer and a silicon nitride layer are sequentially formed on a substrate. The silicon nitride layer and the first oxide layer are then patterned to form an opening, exposing a portion of the substrate. An oxidation process is then conducted to form a second oxide layer on the silicon nitride layer and concurrently to form a field oxide layer on the exposed substrate. The second oxide layer, the silicon nitride layer and the first oxide layer are then patterned to form an oxide dielectric layer, a silicon nitride floating gate layer and a tunnel oxide layer.

    Method of utilizing fabrication process of floating gate spacer to build twin-bit monos/sonos memory
    64.
    发明授权
    Method of utilizing fabrication process of floating gate spacer to build twin-bit monos/sonos memory 有权
    利用浮栅间隔器制造工艺构建双位单声道/声纳存储器的方法

    公开(公告)号：US06551880B1

    公开(公告)日：2003-04-22

    申请号：US10146876

    申请日：2002-05-17

    申请人： Erh-Kun Lai ,  Chien-Hung Liu ,  Shou Wei Huang ,  Shyi-Shuh Pan ,  Ying Tzoo Chen

    发明人： Erh-Kun Lai ,  Chien-Hung Liu ,  Shou Wei Huang ,  Shyi-Shuh Pan ,  Ying Tzoo Chen

    IPC分类号： H01L218247

    CPC分类号： H01L27/11568 ,  H01L21/28282 ,  H01L27/115 ,  H01L29/66833 ,  H01L29/7923

    摘要： The present invention discloses a method of utilizing the fabrication process of floating gate spacer to build a twin-bit MONOS/SONOS memory, wherein recessed ONO spacers are used to fabricate a discontinuous floating gate below a poly control gate to obtain a MONOS/SONOS memory device having twinbit memory cells. Cross talk between charges stored in the two bits can be avoided, hence enhancing the reliability of memory device. Moreover, if the voltage Vt varies during the fabrication process, the device can restore its normal characteristics through the individual and separate characteristic of the two bits and by using program or erase condition. The present invention can utilize the fabrication process of ONO spacer to complete the fabrication process of floating gate in automatic alignment way without the need of undergoing several mask processes.

    摘要翻译： 本发明公开了利用浮栅间隔器的制造工艺来构建双位MONOS / SONOS存储器的方法，其中使用凹入的ONO间隔物来制造多控制栅极下的不连续浮动栅极，以获得MONOS / SONOS存储器 具有双位存储单元的器件。 可以避免存储在两位中的电荷之间的串扰，从而提高存储器件的可靠性。 此外，如果在制造过程中电压Vt变化，则器件可以通过两位的单独和分离的特性以及使用编程或擦除条件恢复其正常特性。 本发明可以利用ONO间隔物的制造工艺以自动对准的方式完成浮栅的制造工艺，而不需要经历多次掩模工艺。

    Method of forming an embedded memory
    65.
    发明授权
    Method of forming an embedded memory 有权
    形成嵌入式存储器的方法

    公开(公告)号：US06448126B1

    公开(公告)日：2002-09-10

    申请号：US09682217

    申请日：2001-08-07

    申请人： Erh-Kun Lai ,  Hsin-Huei Chen ,  Shou-Wei Huang ,  Ying-Tso Chen ,  Chien-Hung Liu ,  Shyi-Shuh Pan

    发明人： Erh-Kun Lai ,  Hsin-Huei Chen ,  Shou-Wei Huang ,  Ying-Tso Chen ,  Chien-Hung Liu ,  Shyi-Shuh Pan

    IPC分类号： H01L218238

    CPC分类号： H01L21/823418 ,  H01L21/823412

    摘要： A method of forming an embedded memory integrating nitride read only memory starts by forming an ONO layer and a protective cap layer on a surface of a semiconductor substrate defined with a memory area and a periphery area. The periphery area has a first, a second and a third device area. An etching and a first ion implantation process form each bit line in the memory area. A spacer is then formed at either side of the protective cap layer and the ONO layer in the memory area, and the protective cap layer and the ONO layer are removed in the first device area. The threshold voltage for the first device area is adjusted and a first thermal oxidation process forms a buried drain oxide layer atop each bit line and a first gate oxide layer on the surface of the first device area, respectively. The protective cap layer and the ONO layer are removed from the second device area and the third device area, and a second gate oxide layer is formed in the second device area and the third device area. Finally, the protective cap layer in the memory area and the second gate oxide layer in the third device area are removed, and a third gate oxide layer is formed in the third device area.

    摘要翻译： 集成氮化物只读存储器的嵌入式存储器的形成方法首先通过在由存储区域和周边区域限定的半导体衬底的表面上形成ONO层和保护覆盖层。 周边区域具有第一，第二和第三设备区域。 蚀刻和第一离子注入工艺在存储区域中形成每个位线。 然后在保护盖层和存储区域中的ONO层的任一侧形成间隔物，并且在第一装置区域中去除保护盖层和ONO层。 调整第一器件区域的阈值电压，第一热氧化工艺分别在第一器件区域的表面上的每个位线和第一栅极氧化物层的顶部形成掩埋的漏极氧化物层。 从第二设备区域和第三设备区域去除保护盖层和ONO层，并且在第二设备区域和第三设备区域中形成第二栅极氧化物层。 最后，去除存储区域中的保护盖层和第三器件区域中的第二栅极氧化物层，并且在第三器件区域中形成第三栅极氧化物层。

    Chip package and method for forming the same
    68.
    发明授权
    Chip package and method for forming the same 有权
    芯片封装及其形成方法

    公开(公告)号：US08975106B2

    公开(公告)日：2015-03-10

    申请号：US13176667

    申请日：2011-07-05

    申请人： Chien-Hung Liu

    发明人： Chien-Hung Liu

    IPC分类号： H01L21/302 ,  H01L21/28 ,  B81C1/00

    CPC分类号： B81C1/00333

    摘要： A method for forming a chip package includes: providing a substrate having a first and a second surfaces; removing a portion of the substrate to form openings in the substrate, wherein the openings extend from the first surface towards the second surface or from the second surface towards the first surface; after forming the openings, at least a first portion of the substrate serves as a first movable bulk, and at least a second portion of the substrate serves as a second movable bulk, wherein the first movable bulk and the second movable bulk are respectively located between the openings; disposing a protecting substrate on the second surface of the substrate; forming a through-hole in the protecting substrate; and forming a conducting layer on the protecting substrate, wherein the conducting layer extends from a surface of the protecting substrate into the through-hole to electrically connect the second movable bulk.

    摘要翻译： 一种用于形成芯片封装的方法，包括：提供具有第一和第二表面的衬底; 去除衬底的一部分以在衬底中形成开口，其中开口从第一表面朝向第二表面或从第二表面朝向第一表面延伸; 在形成开口之后，衬底的至少第一部分用作第一可移动体，并且衬底的至少第二部分用作第二可移动体，其中第一可移动体和第二活动体分别位于 开口; 在衬底的第二表面上设置保护衬底; 在保护衬底中形成通孔; 以及在所述保护衬底上形成导电层，其中所述导电层从所述保护衬底的表面延伸到所述通孔中以电连接所述第二可移动体。

    Common repair structures for close bus in a liquid crystal display
    69.
    发明授权
    Common repair structures for close bus in a liquid crystal display 有权
    常用的液晶显示器关闭总线修复结构

    公开(公告)号：US08724062B2

    公开(公告)日：2014-05-13

    申请号：US13549798

    申请日：2012-07-16

    申请人： Chien-Hung Liu

    发明人： Chien-Hung Liu

    IPC分类号： G02F1/1337 ,  G02F1/1362

    CPC分类号： G02F1/136259 ,  G02F2001/136263

    摘要： One aspect of the present disclosure relates to a common repair structure for repairing scanning and/or data line defects in a liquid crystal display panel. In one embodiment, the common repair structure includes a plurality of “H” shaped structures, where each “H” shaped structure is placed over a corresponding segment of two neighboring scanning lines located between and associated with two neighboring pixels along the second direction or a corresponding segment of two neighboring data lines located between and associated with two neighboring pixels along the first direction.

    摘要翻译： 本公开的一个方面涉及用于修复液晶显示面板中的扫描和/或数据线缺陷的常见修复结构。 在一个实施例中，公共修复结构包括多个“H”形结构，其中每个“H”形结构被放置在沿着第二方向位于两个相邻像素之间并与之相关联的两个相邻扫描线的对应段上，或者 两个相邻数据线的对应段位于沿着第一方向的两个相邻像素之间并与之相关联。