公开(公告)号：US20190206682A1

公开(公告)日：2019-07-04

申请号：US15860161

申请日：2018-01-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xunyuan ZHANG ,  Ruilong XIE ,  Yi QI

IPC: H01L21/033 ,  H01L21/02

CPC classification number: H01L21/0335 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/0332

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to cut margin structures and methods of manufacture. The method includes: forming a plurality of patterned hardmask stacks containing at least a semiconductor layer and a capping layer; removing a portion of a first patterned hardmask stack and a margin of an adjacent hardmask stack of the plurality of the patterned hardmask stacks; and selectively growing material on the margin of the adjacent hardmask stack.

公开(公告)号：US20190139830A1

公开(公告)日：2019-05-09

申请号：US15802795

申请日：2017-11-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong XIE ,  Minoli K. PATHIRANE ,  Chanro PARK ,  Guillaume BOUCHE ,  Nigel CAVE ,  Mahender KUMAR ,  Min Gyu SUNG ,  Huang LIU ,  Hui ZANG

IPC: H01L21/8234 ,  H01L27/092 ,  H01L27/088 ,  H01L29/06 ,  H01L21/768 ,  H01L21/311 ,  H01L21/02 ,  H01L29/78

Abstract: Fin field effect transistors (FinFETs) and their methods of manufacture include a self-aligned gate isolation layer. A method of forming the FinFETs includes the formation of sacrificial spacers over fin sidewalls, and the formation of an isolation layer between adjacent fins at self-aligned locations between the sacrificial spacers. An additional layer such as a sacrificial gate layer is formed over the isolation layer, and photolithography and etching techniques are used to cut, or segment, the additional layer to define a gate cut opening over the isolation layer. The gate cut opening is backfilled with a dielectric material, and the backfilled dielectric and the isolation layer cooperate to separate neighboring sacrificial gates and hence the later-formed functional gates associated with respective devices.

公开(公告)号：US20180374935A1

公开(公告)日：2018-12-27

申请号：US16056934

申请日：2018-08-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Cheng CHI ,  Fee Li LIE ,  Chi-Chun LIU ,  Ruilong XIE

IPC: H01L29/66 ,  H01L21/3105 ,  H01L21/033 ,  H01L29/06 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/51 ,  H01L21/3065 ,  H01L21/308 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/22 ,  H01L29/49

CPC classification number: H01L29/66795 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/31051 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/22 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7851 ,  H01L29/7853

Abstract: A method for fabricating a semiconductor device comprises forming a first hardmask, a planarizing layer, and a second hardmask on a substrate. Removing portions of the second hardmask and forming alternating blocks of a first material and a second material over the second hardmask. The blocks of the second material are removed to expose portions of the planarizing layer. Exposed portions of the planarizing layer and the first hardmask are removed to expose portions of the first hardmask. Portions of the first hardmask and portions of the substrate are removed to form a first fin and a second fin. Portions of the substrate are removed to further increase the height of the first fin and substantially remove the second fin. A gate stack is formed over a channel region of the first fin.

公开(公告)号：US20180233412A1

公开(公告)日：2018-08-16

申请号：US15433188

申请日：2017-02-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong XIE ,  Daniel CHANEMOUGAME ,  Lars LIEBMANN ,  Nigel CAVE

IPC: H01L21/8234 ,  H01L21/285 ,  H01L27/088 ,  H01L29/78

CPC classification number: H01L21/823425 ,  H01L21/28518 ,  H01L21/823431 ,  H01L21/823475 ,  H01L27/0886 ,  H01L29/785 ,  H01L2029/7858

Abstract: A method of forming a logic or memory cell with less than or equal to 0 nm of TS extending past the active fins and the resulting device are provided. Embodiments include forming gates across pairs of fins on a substrate; forming pairs of RSD between the gates on the fins; forming a planar SAC cap on each of the gates; forming a metal layer over the substrate coplanar with the SACs; forming a TS structure in the metal layer over the fins, the TS structure formed over the pairs of RSD, each upper portion having a width equal to or less than an overall width of a pair of fins; forming spacers on opposite sides of the upper portions; removing the metal layer between adjacent spacers; forming an ILD over the substrate; and forming a CA on each upper portion and a CB on a gate through the ILD.

公开(公告)号：US20180122644A1

公开(公告)日：2018-05-03

申请号：US15339497

申请日：2016-10-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong XIE ,  Min Gyu SUNG ,  Chanro PARK ,  Hoon KIM

IPC: H01L21/28 ,  H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L21/768

Abstract: A method includes providing a starting semiconductor structure, the starting semiconductor structure including a semiconductor substrate with active region(s) separated by isolation regions, the active region(s) including source/drain regions of epitaxial semiconductor material, dummy gate structures adjacent each source/drain region, the dummy gate structures including dummy gate electrodes with spacers adjacent opposite sidewalls thereof and gate caps thereover, and openings between the dummy gate structures. The method further includes filling the openings with a dielectric material, recessing the dielectric material, resulting in a filled and recessed structure, and forming a hard mask liner layer over the filled and recessed structure to protect against loss of the recessed dielectric material during subsequent removal of unwanted dummy gate electrodes. A resulting semiconductor structure formed by the method is also provided.

公开(公告)号：US20180090374A1

公开(公告)日：2018-03-29

申请号：US15817554

申请日：2017-11-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES, INC.

Inventor： Cheng CHI ,  Ruilong XIE

IPC: H01L21/768 ,  H01L29/45 ,  H01L29/417 ,  H01L29/06 ,  H01L27/088 ,  H01L23/532 ,  H01L23/528 ,  H01L23/522 ,  H01L21/8234

CPC classification number: H01L21/76897 ,  H01L21/76802 ,  H01L21/76808 ,  H01L21/76877 ,  H01L21/823475 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53228 ,  H01L23/53257 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/41766 ,  H01L29/45

Abstract: Techniques relate to contacts for semiconductors. First gate contacts are formed on top of first gates, second gate contacts are on second gates, and terminal contacts are on silicide contacts. First gate contacts and terminal contacts are recessed to form a metal layer on top. Second gate contacts are recessed to be separately on each of the second gates. Filling material is formed on top of the recessed second gate contacts and metal layer. An upper layer is on top of the filling material. First metal vias are formed through filling and upper layers down to metal layer over first gate contacts. Second metal vias are formed through filling and upper layers down to metal layer over terminal contacts. Third metal vias are formed through filling and upper layers down to recessed second gate contacts over second gates. Third metal vias are taller than first.

公开(公告)号：US20180019337A1

公开(公告)日：2018-01-18

申请号：US15683228

申请日：2017-08-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong XIE ,  Chanro PARK ,  Min Gyu SUNG ,  Hoon KIM

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/49 ,  H01L29/08 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/324 ,  H01L29/66 ,  H01L21/28

CPC classification number: H01L29/7827 ,  H01L21/28088 ,  H01L21/324 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823487 ,  H01L21/823814 ,  H01L21/823885 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66666

Abstract: An intermediate semiconductor structure in fabrication includes a silicon semiconductor substrate, a hard mask of silicon nitride (SiN) over the substrate and a sacrificial layer of polysilicon or amorphous silicon over the hard mask. The sacrificial layer is patterned into sidewall spacers, each of the sidewall spacers having vertically tapered inner and outer sidewalls providing a rough triangular shape. The rough triangular sidewall spacers are used as a temporary hard mask to pattern the SiN hard mask.

公开(公告)号：US20170309522A1

公开(公告)日：2017-10-26

申请号：US15645395

申请日：2017-07-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chanro PARK ,  Min Gyu SUNG ,  Hoon KIM ,  Ruilong XIE

IPC: H01L21/8238 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L21/823821 ,  H01L21/02112 ,  H01L21/02115 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/31056 ,  H01L21/31116 ,  H01L21/823807 ,  H01L21/823892 ,  H01L29/66795

Abstract: A method includes providing a substrate having a first and a second plurality of fins with a first at least one dielectric material disposed thereon, removing upper portions of the first dielectric material to expose upper portions of the first and the second plurality of fins, removing the first dielectric material from the lower portions of the second plurality of fins to expose lower portions of the second plurality of fins, depositing a second at least one dielectric material on at least the upper and the lower exposed portions of the second plurality of fins and on the upper exposed portions of first plurality of fins, removing the second dielectric material to expose upper portions of the first and the second plurality of fins, and wherein the first dielectric material is different from the second dielectric material. The resulting structure may be operable for use as nFETs and pFETs.

公开(公告)号：US20170271163A1

公开(公告)日：2017-09-21

申请号：US15072626

申请日：2016-03-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min Gyu SUNG ,  Ruilong XIE ,  Chanro PARK ,  Hoon KIM ,  Kwan-Yong LIM

IPC: H01L21/3065 ,  H01L29/161 ,  H01L27/11 ,  H01L29/06 ,  H01L21/311 ,  H01L21/308

CPC classification number: H01L21/3065 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/31144 ,  H01L27/11 ,  H01L28/00 ,  H01L29/0642 ,  H01L29/0657 ,  H01L29/161

Abstract: Methodologies and a device for SRAM patterning are provided. Embodiments include forming a spacer layer over a fin channel, the fin channel being formed in four different device regions; forming a bottom mandrel over the spacer layer; forming a top mandrel directly over the bottom mandrel, wherein the top and bottom mandrels including different materials; forming a buffer oxide layer over the top mandrel; forming an anti-reflective coating (ARC) over the first OPL; forming a photoresist (PR) over the ARC and patterning the PR; and etching the first OPL, ARC, buffer oxide, and top mandrel with the pattern of the PR, wherein a pitch of the PR as patterned is different in each of the four device regions.

公开(公告)号：US20170256624A1

公开(公告)日：2017-09-07

申请号：US15060761

申请日：2016-03-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Tek Po Rinus LEE ,  Jinping LIU ,  Ruilong XIE

IPC: H01L29/47 ,  H01L21/266 ,  H01L21/8238 ,  H01L21/285 ,  H01L29/40 ,  H01L27/092

CPC classification number: H01L29/47 ,  H01L21/26506 ,  H01L21/266 ,  H01L21/28518 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/092 ,  H01L29/401 ,  H01L29/78

Abstract: Methods for forming a semiconductor device having dual Schottky barrier heights using a single metal and the resulting device are provided. Embodiments include providing a substrate having an n-FET region and a p-FET region, each region including a gate between source/drain regions; applying a mask over the n-FET region; selectively amorphizing a surface of the p-FET region source/drain regions while the n-FET region is masked; removing the mask; depositing a titanium-based metal over the n-FET and p-FET region source/drain regions; and microwave annealing.