公开(公告)号：US09490018B2

公开(公告)日：2016-11-08

申请号：US14679574

申请日：2015-04-06

Applicant: Intel Corporation

Inventor： Yogesh B. Wakchaure ,  Kiran Pangal ,  Xin Guo ,  Qingru Meng ,  Hanmant P. Belgal

IPC: G11C16/16 ,  G11C16/14 ,  G11C16/06 ,  G11C16/04 ,  G11C16/34 ,  G11C16/10 ,  G11C29/02 ,  G11C16/26 ,  H01L27/115

CPC classification number: G11C16/14 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/10 ,  G11C16/102 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3418 ,  G11C16/3445 ,  G11C29/028 ,  H01L27/115

Abstract: A flash memory device may include two or more flash memory cells organized as a NAND string in a block of flash memory cells, and flash cells, coupled to the NAND string at opposite ends, to function as select gates. The flash memory device may be capable of providing information related to a voltage threshold of the select gates to a flash controller, erasing the flash cells that function as select gates in response to a select gate erase command, and programming the flash cells that function as select gates in response to a select gate program command. A flash controller may be coupled to the flash memory device, and is capable of sending the select gate erase commend to the flash memory device if the information provided by the flash memory device indicates that the voltage threshold of at least one of the select gates is above a predetermined voltage level, and sending the select gate program command to the flash memory device if the information provided by the flash memory device indicates that the voltage threshold of at least one of the select gates is outside of a predetermined voltage range.

公开(公告)号：US09478286B1

公开(公告)日：2016-10-25

申请号：US14998179

申请日：2015-12-26

Applicant: Intel Corporation

Inventor： Davide Mantegazza ,  Sandeep Guliani ,  Balaji Srinivasan ,  Kiran Pangal

IPC: G11C11/00 ,  G11C13/00

CPC classification number: G11C13/0004 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0033 ,  G11C13/004 ,  G11C29/70

Abstract: Threshold switching devices demonstrating transient current protection through both insulation and repair current mechanisms, including associated systems and methods, are provided and discussed.

Abstract translation: 提供并讨论了通过绝缘和修复电流机制（包括相关系统和方法）演示瞬态电流保护的阈值开关器件。

公开(公告)号：US20160217853A1

公开(公告)日：2016-07-28

申请号：US14846898

申请日：2015-09-07

Applicant: Intel Corporation

Inventor： Sandeep K. Guliani ,  Kiran Pangal ,  Balaji Srinivasan ,  Chaohong Hu

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C7/00 ,  G11C8/08 ,  G11C8/14 ,  G11C11/16 ,  G11C11/1653 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1673 ,  G11C11/419 ,  G11C11/5678 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/003

Abstract: A multistage read can dynamically change wordline capacitance as a function of threshold voltage of a memory cell being read. The multistage read can reduce current spikes and reduce the heating up of a memory cell during a read. A memory device includes a global wordline driver to connect a wordline of a selected memory cell to the sensing circuit, and a local wordline driver local to the memory cell. After the wordline is charged to a read voltage, control logic can selectively enable and disable a portion or all of the global wordline driver and the local wordline driver in conjunction with applying different discrete voltage levels to the bitline to perform a multistage read.

Abstract translation: 多级读取可以根据读取的存储器单元的阈值电压动态地改变字线电容。 多级读取可以减少电流尖峰，并减少读取期间存储单元的加热。 存储器件包括用于将所选择的存储器单元的字线连接到感测电路的全局字线驱动器，以及存储器单元本地的本地字线驱动器。 在字线被充电到读取电压之后，控制逻辑可以选择性地启用和禁用全局字线驱动器和本地字线驱动器的一部分或全部，同时将不同的离散电压电平应用于位线以执行多级读取。

公开(公告)号：US20160188409A1

公开(公告)日：2016-06-30

申请号：US14844843

申请日：2015-09-03

Applicant: Intel Corporation

Inventor： Kiran Pangal ,  Prashant S. Damle ,  Rajesh Sundaram ,  Shekoufeh Qawami ,  Julie M. Walker ,  Doyle Rivers

IPC: G06F11/10 ,  G06F3/06

CPC classification number: G06F11/1076 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/1044 ,  G06F11/1048 ,  G06F11/1068 ,  H03M13/05 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/19 ,  H03M13/27 ,  H03M13/6508

Abstract: Uncorrectable memory errors may be reduced by determining a logical array address for a set of memory arrays and transforming the logical array address to at least two unique array addresses based, at least in part, on logical locations of at least two memory arrays within the set of memory arrays. The at least two memory arrays are then accessed using the at least two unique array addresses, respectively.

Abstract translation: 可以通过确定一组存储器阵列的逻辑阵列地址并且至少部分地基于该组内的至少两个存储器阵列的逻辑位置将逻辑阵列地址变换为至少两个唯一阵列地址来减少不可校正的存储器错误 的存储器阵列。 然后使用至少两个唯一的阵列地址分别访问至少两个存储器阵列。

公开(公告)号：US09317364B2

公开(公告)日：2016-04-19

申请号：US14129066

申请日：2013-09-25

Applicant: INTEL CORPORATION

Inventor： Ravi H. Motwani ,  Kiran Pangal

IPC: G11C29/00 ,  G06F11/10 ,  G06F13/16

CPC classification number: G06F11/1076 ,  G06F11/1012 ,  G06F13/16 ,  G06F13/1694 ,  G11C7/1006 ,  G11C13/0004 ,  G11C13/0069

Abstract: Methods, apparatuses, and systems are described related to memory controllers for memory. In one embodiment, a memory controller may include a distribution transformer configured to receive data to be stored into a memory, wherein the data has a distribution of m1:n1 ratio for bits having a first logic value and bits having a second logic value, where m1 and n1 are real numbers. The distribution transformer may transform the data into skewed data, wherein the skewed data has a distribution of m2:n2 ratio for bits having the first logic value and bits having the second logic value, where m2 and n2 are real numbers that are different from one another and respectively differ from m1 and n1. The distribution transformer may output the skewed data for storage in the memory. Other embodiments may be described and claimed.

Abstract translation: 描述与存储器的存储器控​​制器相关的方法，装置和系统。 在一个实施例中，存储器控制器可以包括被配置为接收要存储到存储器中的数据的分配变压器，其中所述数据具有用于具有第一逻辑值的位和具有第二逻辑值的位的m1：n1比率分布，其中 m1和n1是实数。 分配变压器可以将数据变换成偏斜数据，其中偏斜数据具有具有第一逻辑值的比特的m2：n2比率和具有第二逻辑值的比特的分布，其中m2和n2是不同于一个的实数 另一个，分别不同于m1和n1。 配电变压器可以输出偏斜数据以存储在存储器中。 可以描述和要求保护其他实施例。

公开(公告)号：US09257175B2

公开(公告)日：2016-02-09

申请号：US14038165

申请日：2013-09-26

Applicant: INTEL CORPORATION

Inventor： Kiran Pangal ,  Raj K. Ramanujan ,  Robert W. Faber ,  Rajesh Sundaram

IPC: G06F13/12 ,  G11C11/00 ,  G11C13/00

CPC classification number: G11C13/0033 ,  G11C13/0004 ,  G11C2013/0076

Abstract: Embodiments including systems, methods, and apparatuses associated with refreshing memory cells are disclosed herein. In embodiments, a memory controller may be configured to perform a read operation on one or more memory cells in a cross-point non-volatile memory such as a phase change memory (PCM). The one or more memory cells may have voltage values respectively set to a first threshold voltage or a second threshold voltage. Based on the read, the memory controller may identify the memory cells in the cross-point non-volatile memory that are set to the second threshold voltage, and refresh the voltage values of those cells without altering the voltage values of the memory cells in the cross-point non-volatile memory that are set to the first threshold voltage. Other embodiments may be described or claimed.

Abstract translation: 本文公开了包括与刷新存储器单元相关联的系统，方法和装置的实施例。 在实施例中，存储器控制器可以被配置为对诸如相变存储器（PCM）的交叉点非易失性存储器中的一个或多个存储器单元执行读取操作。 一个或多个存储单元可以具有分别设置为第一阈值电压或第二阈值电压的电压值。 基于读取，存储器控制器可以识别被设置为第二阈值电压的交叉点非易失性存储器中的存储器单元，并且在不改变这些存储器单元的电压值的情况下刷新那些单元的电压值 交叉点非易失性存储器被设置为第一阈值电压。 可以描述或要求保护其他实施例。

公开(公告)号：US09202547B2

公开(公告)日：2015-12-01

申请号：US13832278

申请日：2013-03-15

Applicant: Intel Corporation

Inventor： Prashant S. Damle ,  Frank T. Hady ,  Paul D. Ruby ,  Kiran Pangal ,  Sowmiya Jayachandran

IPC: G06F12/16 ,  G11C11/406 ,  G11C16/34

CPC classification number: G11C7/1072 ,  G11C11/406 ,  G11C11/40618 ,  G11C16/3431

Abstract: In an embodiment, a memory controller may determine that one or more neighboring memory cells associated with a target memory cell in a memory device are to be refreshed. The controller may generate a command associated with refreshing the one or more neighboring memory cells. The controller may transfer the command from the memory controller to the memory device containing the target memory cell. The command may direct the memory device to refresh the neighboring memory cells and/or return one or more addresses associated with the neighboring memory cells.

Abstract translation: 在一个实施例中，存储器控制器可以确定与存储器件中的目标存储器单元相关联的一个或多个相邻存储器单元将被刷新。 控制器可以生成与刷新一个或多个相邻存储器单元相关联的命令。 控制器可以将命令从存储器控制器传送到包含目标存储器单元的存储器件。 命令可以指示存储器设备刷新相邻存储器单元和/或返回与相邻存储器单元相关联的一个或多个地址。

公开(公告)号：US09037943B2

公开(公告)日：2015-05-19

申请号：US13662160

申请日：2012-10-26

Applicant: INTEL CORPORATION

Inventor： Ravi H. Motwani ,  Kiran Pangal

IPC: H03M13/00 ,  H03M13/29 ,  H03M13/09 ,  H03M13/11

CPC classification number: H03M13/2927 ,  H03M13/09 ,  H03M13/1102 ,  H03M13/293 ,  H03M13/2948 ,  H03M13/2957

Abstract: Embodiments of apparatus, methods, storage drives, computer-readable media, systems and devices are described herein for identification of die of non-volatile memory for use in remedial action. In various embodiments, a first block may be configured to encode data to be stored in a non-volatile memory as a codeword. In various embodiments, the first block may be configured to store respective portions of the codeword in a distributed manner across a plurality of die of the non-volatile memory. In various embodiments, the first block may be configured to generate respective error detection codes for the plurality of die.

Abstract translation: 本文描述了装置，方法，存储驱动器，计算机可读介质，系统和设备的实施例，用于识别用于补救动作的非易失性存储器的管芯。 在各种实施例中，第一块可以被配置为将要存储在非易失性存储器中的数据编码为码字。 在各种实施例中，第一块可以被配置为以分布式方式存储码字的相应部分跨越非易失性存储器的多个管芯。 在各种实施例中，第一块可以被配置为为多个管芯生成相应的检错代码。

公开(公告)号：US20150089120A1

公开(公告)日：2015-03-26

申请号：US14038165

申请日：2013-09-26

Applicant: INTEL CORPORATION

Inventor： Kiran Pangal ,  Raj K. Ramanujan ,  Robert W. Faber ,  Rajesh Sundaram

IPC: G11C14/00

CPC classification number: G11C13/0033 ,  G11C13/0004 ,  G11C2013/0076

Abstract: Embodiments including systems, methods, and apparatuses associated with refreshing memory cells are disclosed herein. In embodiments, a memory controller may be configured to perform a read operation on one or more memory cells in a cross-point non-volatile memory such as a phase change memory (PCM). The one or more memory cells may have voltage values respectively set to a first threshold voltage or a second threshold voltage. Based on the read, the memory controller may identify the memory cells in the cross-point non-volatile memory that are set to the second threshold voltage, and refresh the voltage values of those cells without altering the voltage values of the memory cells in the cross-point non-volatile memory that are set to the first threshold voltage. Other embodiments may be described or claimed.

Abstract translation: 本文公开了包括与刷新存储器单元相关联的系统，方法和装置的实施例。 在实施例中，存储器控制器可以被配置为对诸如相变存储器（PCM）的交叉点非易失性存储器中的一个或多个存储器单元执行读取操作。 一个或多个存储单元可以具有分别设置为第一阈值电压或第二阈值电压的电压值。 基于读取，存储器控制器可以识别被设置为第二阈值电压的交叉点非易失性存储器中的存储器单元，并且在不改变这些存储器单元的电压值的情况下刷新那些单元的电压值 交叉点非易失性存储器被设置为第一阈值电压。 可以描述或要求保护其他实施例。

公开(公告)号：US08959407B2

公开(公告)日：2015-02-17

申请号：US13687951

申请日：2012-11-28

Applicant: Intel Corporation

Inventor： Ravi H. Motwani ,  Kiran Pangal

IPC: G06F11/00 ,  H03M13/13 ,  H03M13/37 ,  H03M13/00 ,  G06F11/10 ,  H03M13/11 ,  H03M13/29

CPC classification number: H03M13/13 ,  G06F11/1012 ,  H03M13/1102 ,  H03M13/29 ,  H03M13/2957 ,  H03M13/3723 ,  H03M13/3746 ,  H03M13/612 ,  H03M13/6337

Abstract: Embodiments include methods, apparatuses, and instructions for encoding a codeword of data as codeword portions stored across multiple die in a non-volatile memory. Embodiments further include a decoder which may be configured to decode the portions of the codeword using hard decision reads. The decoder may then be configured to estimate the quality of each die, and apply a scaling factor to the decoded codeword portions such that confidence or reliability information can be determined for the codeword.

Abstract translation: 实施例包括用于将数据的码字编码为在非易失性存储器中跨多个存储器存储的码字部分的方法，装置和指令。 实施例还包括解码器，其可以被配置为使用硬判决读取对码字的部分进行解码。 解码器然后可以被配置为估计每个管芯的质量，并将缩放因子应用于解码的码字部分，使得可以为码字确定置信度或可靠性信息。