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    THICK BOND PAD FOR CHIP WITH CAVITY PACKAGE
    61.
    发明申请
    THICK BOND PAD FOR CHIP WITH CAVITY PACKAGE 有权
    厚重的包装用于芯片

    公开(公告)号：US20110068424A1

    公开(公告)日：2011-03-24

    申请号：US12564996

    申请日：2009-09-23

    申请人： Jeffrey P. Gambino ,  Robert K. Leidy ,  Richard J. Rassel

    发明人： Jeffrey P. Gambino ,  Robert K. Leidy ,  Richard J. Rassel

    IPC分类号： H01L31/0232

    CPC分类号： H01L27/14687 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/5384 ,  H01L31/0203 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Disclosed herein an image sensor chip, including a substrate having at least one via extending through at least one inter layer dielectric (ILD); a first conductive layer over the ILD, wherein the first conductive layer has a first thickness; a second conductive layer over the first conductive layer, wherein the second conductive layer has a second thickness of less than the first thickness; a polymer layer over the second conductive layer, the polymer layer including a cavity; a plurality of cavity components in the cavity; and an optically transparent layer contacting the polymer layer and covering the cavity.

    摘要翻译： 本文公开了一种图像传感器芯片，包括具有延伸穿过至少一个层间电介质（ILD）的至少一个通孔的基板; ILD上的第一导电层，其中所述第一导电层具有第一厚度; 在所述第一导电层上的第二导电层，其中所述第二导电层具有小于所述第一厚度的第二厚度; 在所述第二导电层上的聚合物层，所述聚合物层包括空腔; 空腔中的多个空腔部件; 以及与聚合物层接触并覆盖空腔的光学透明层。

    CMOS imager with Cu wiring and method of eliminating high reflectivity interfaces therefrom
    63.
    发明授权
    CMOS imager with Cu wiring and method of eliminating high reflectivity interfaces therefrom 失效
    具有Cu布线的CMOS成像器和从其中消除高反射率界面的方法

    公开(公告)号：US07772028B2

    公开(公告)日：2010-08-10

    申请号：US11959841

    申请日：2007-12-19

    申请人： James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Richard J. Rassel ,  Anthony K. Stamper

    发明人： James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Richard J. Rassel ,  Anthony K. Stamper

    IPC分类号： H01L21/66

    CPC分类号： H01L27/14636 ,  H01L21/76819 ,  H01L21/76834 ,  H01L27/14621 ,  H01L27/14625 ,  H01L27/14627 ,  H01L27/14629 ,  H01L27/14645 ,  H01L27/14683

    摘要： A CMOS image sensor and method of fabrication wherein the sensor includes Copper (Cu) metallization levels allowing for incorporation of a thinner interlevel dielectric stack to result in a pixel array exhibiting increased light sensitivity. The CMOS image sensor includes structures having a minimum thickness of barrier layer metal that traverses the optical path of each pixel in the sensor array or, that have portions of barrier layer metal selectively removed from the optical paths of each pixel, thereby minimizing reflectance. That is, by implementing various block or single mask methodologies, portions of the barrier layer metal are completely removed at locations of the optical path for each pixel in the array. In a further embodiment, the barrier metal layer may be formed atop the Cu metallization by a self-aligned deposition.

    摘要翻译： CMOS图像传感器和制造方法，其中传感器包括铜（Cu）金属化水平，允许结合较薄的层间电介质堆叠以产生呈现增加的光灵敏度的像素阵列。 CMOS图像传感器包括具有穿过传感器阵列中的每个像素的光路的阻挡层金属的最小厚度的结构，或者具有从每个像素的光路中选择性地去除的阻挡层金属的部分，从而使反射率最小化的结构。 也就是说，通过实现各种块或单掩模方法，在阵列中的每个像素的光路的位置处完全去除了阻挡层金属的部分。 在另一个实施例中，阻挡金属层可以通过自对准沉积形成在Cu金属化之上。

    VERTICAL METAL-INSULATOR-METAL (MIM) CAPACITOR USING GATE STACK, GATE SPACER AND CONTACT VIA
    65.
    发明申请
    VERTICAL METAL-INSULATOR-METAL (MIM) CAPACITOR USING GATE STACK, GATE SPACER AND CONTACT VIA 有权
    垂直金属绝缘子金属（MIM）电容器使用盖板，隔板和接触器

    公开(公告)号：US20100163949A1

    公开(公告)日：2010-07-01

    申请号：US12344697

    申请日：2008-12-29

    申请人： Ramachandra Divakaruni ,  Mukta G. Farooq ,  Jeffrey P. Gambino ,  Kevin S. Petrarca

    发明人： Ramachandra Divakaruni ,  Mukta G. Farooq ,  Jeffrey P. Gambino ,  Kevin S. Petrarca

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L28/60 ,  H01L21/76897 ,  H01L23/485 ,  H01L27/0629 ,  H01L27/0805 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor structure including a vertical metal-insulator-metal capacitor, and a method for fabricating the semiconductor structure including the vertical metal-insulator-metal capacitor, each use structural components from a dummy metal oxide semiconductor field effect transistor located and formed over an isolation region located over a semiconductor substrate. The dummy metal oxide field effect transistor may be formed simultaneously with a metal oxide semiconductor field effect transistor located over a semiconductor substrate that includes the isolation region. The metal-insulator-metal capacitor uses a gate as a capacitor plate, a uniform thickness gate spacer as a gate dielectric and a contact via as another capacitor plate. The uniform thickness gate spacer may include a conductor layer for enhanced capacitance. A mirrored metal-insulator-metal capacitor structure that uses a single contact via may also be used for enhanced capacitance.

    摘要翻译： 包括垂直金属 - 绝缘体 - 金属电容器的半导体结构以及包括垂直金属 - 绝缘体 - 金属电容器的半导体结构的制造方法，每个都使用位于隔离层上并形成的虚设金属氧化物半导体场效应晶体管的结构部件 区域位于半导体衬底上。 虚拟金属氧化物场效应晶体管可以与位于包括隔离区域的半导体衬底之上的金属氧化物半导体场效应晶体管同时形成。 金属 - 绝缘体 - 金属电容器使用栅极作为电容器板，均匀厚度的栅极间隔物作为栅极电介质和作为另一个电容器板的接触通孔。 均匀厚度的栅极间隔物可以包括用于增强电容的导体层。 使用单个接触通孔的镜像金属 - 绝缘体 - 金属电容器结构也可用于增强电容。

    Pixel sensor with reduced image lag
    67.
    发明授权
    Pixel sensor with reduced image lag 有权
    具有降低图像滞后的像素传感器

    公开(公告)号：US07732845B2

    公开(公告)日：2010-06-08

    申请号：US12099339

    申请日：2008-04-08

    申请人： James W Adkisson ,  Jeffrey P. Gambino ,  Rajendran Krishnasamy ,  Solomon Mulugeta

    发明人： James W Adkisson ,  Jeffrey P. Gambino ,  Rajendran Krishnasamy ,  Solomon Mulugeta

    IPC分类号： H01L31/062

    CPC分类号： H01L27/14603

    摘要： A tensile-stress-generating structure is formed above a gate electrode in a CMOS image sensor to apply a normal tensile stress between a charge collection well of a photodiode, which is also a source region of a transfer transistor, and a floating drain in the direction connecting the source region and the floating drain. The tensile stress lowers the potential barrier between the source region and the body of the transfer transistor to effect a faster and more through transfer of the electrical charges in the source region to the floating drain. Image lag is thus reduced in the CMOS image sensor. Further, charge capacity of the source region is also enhanced due to the normal tensile stress applied to the source region.

    摘要翻译： 在CMOS图像传感器的栅电极上方形成拉伸应力产生结构，以在也是转移晶体管的源极区域的光电二极管的电荷收集阱和浮动漏极之间施加正常的拉伸应力 连接源极区域和浮动漏极的方向。 拉伸应力降低了源区域和转移晶体管的主体之间的势垒，以实现更快和更多地将源区域中的电荷转移到浮动漏极。 因此CMOS图像传感器中的图像滞后减少。 此外，由于施加到源极区域的正常拉伸应力，源极区域的充电容量也增强​​。

    Damascene copper wiring optical image sensor
    69.
    发明授权
    Damascene copper wiring optical image sensor 有权
    大马士革铜线接线光学图像传感器

    公开(公告)号：US07655495B2

    公开(公告)日：2010-02-02

    申请号：US11623977

    申请日：2007-01-17

    申请人： James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Anthony K. Stamper

    发明人： James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Anthony K. Stamper

    IPC分类号： H01L21/00

    CPC分类号： H01L27/14685 ,  H01L21/76819 ,  H01L21/76834 ,  H01L21/76838 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/14687

    摘要： A CMOS image sensor array and method of fabrication wherein the sensor includes Copper (Cu) metallization levels allowing for incorporation of a thinner interlevel dielectric stack with improved thickness uniformity to result in a pixel array exhibiting increased light sensitivity. In the sensor array, each Cu metallization level includes a Cu metal wire structure formed at locations between each array pixel and, a barrier material layer is formed on top each Cu metal wire structure that traverses the pixel optical path. By implementing a single mask or self-aligned mask methodology, a single etch is conducted to completely remove the interlevel dielectric and barrier layers that traverse the optical path. The etched opening is then refilled with dielectric material. Prior to depositing the refill dielectric, a layer of either reflective or absorptive material is formed along the sidewalls of the etched opening to improve sensitivity of the pixels by either reflecting light to the underlying photodiode or by eliminating light reflections.

    摘要翻译： CMOS图像传感器阵列和制造方法，其中传感器包括铜（Cu）金属化水平，允许结合更薄的层间电介质叠层，具有改进的厚度均匀性，以产生呈现增加的光敏度的像素阵列。 在传感器阵列中，每个Cu金属化层包括在每个阵列像素之间的位置处形成的Cu金属线结构，并且阻挡材料层形成在穿过像素光路的每个Cu金属线结构上。 通过实现单掩模或自对准掩模方法，进行单次蚀刻以完全去除穿过光路的层间电介质层和阻挡层。 然后将蚀刻的开口用电介质材料重新填充。 在沉积再充填电介质之前，沿蚀刻开口的侧壁形成反射或吸收材料层，以通过将光反射到下面的光电二极管或通过消除光反射来提高像素的灵敏度。