公开(公告)号：US09466361B2

公开(公告)日：2016-10-11

申请号：US14518810

申请日：2014-10-20

Applicant: Micron Technology Inc.

Inventor： Chandra Mouli

IPC: G11C11/36 ,  G11C13/00 ,  G11C11/56 ,  H01L27/24 ,  H01L45/00 ,  G11C5/02 ,  G11C11/34

CPC classification number: H01L27/2418 ,  G11C5/02 ,  G11C11/34 ,  G11C11/39 ,  G11C11/4026 ,  G11C11/5664 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0014 ,  G11C13/0016 ,  G11C13/003 ,  G11C2013/009 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/76 ,  G11C2216/08 ,  H01L29/6609 ,  H01L45/00 ,  H01L45/141 ,  H01L45/145 ,  H01L45/16

Abstract: Some embodiments include memory devices having a wordline, a bitline, a memory element selectively configurable in one of three or more different resistive states, and a diode configured to allow a current to flow from the wordline through the memory element to the bitline responsive to a voltage being applied across the wordline and the bitline and to decrease the current if the voltage is increased or decreased. Some embodiments include memory devices having a wordline, a bitline, memory element selectively configurable in one of two or more different resistive states, a first diode configured to inhibit a first current from flowing from the bitline to the wordline responsive to a first voltage, and a second diode comprising a dielectric material and configured to allow a second current to flow from the wordline to the bitline responsive to a second voltage.

Abstract translation: 一些实施例包括具有字线，位线，可选择性地以三种或更多种不同电阻状态中的一种状态配置的存储器元件的存储器件，以及被配置为允许电流从字线通过存储器元件流过到位线的二极管， 电压施加在字线和位线之间，并且如果电压增加或减小则降低电流。 一些实施例包括具有字线，位线，可选择性地以两种或多种不同电阻状态之一配置的存储器元件的存储器件，被配置为阻止第一电流响应于第一电压从位线流向字线的第一二极管，以及 第二二极管，包括电介质材料，并被配置为响应于第二电压允许第二电流从字线流到位线。

公开(公告)号：US09397187B2

公开(公告)日：2016-07-19

申请号：US14543349

申请日：2014-11-17

Applicant: Micron Technology, Inc.

Inventor： Gurtej S. Sandhu ,  Chandra Mouli

IPC: H01L21/28 ,  H01L21/44 ,  H01L29/66 ,  B82Y10/00 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/872 ,  H01L45/00 ,  H01L49/02

CPC classification number: H01L29/66151 ,  B82Y10/00 ,  H01L21/28 ,  H01L21/283 ,  H01L28/90 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66143 ,  H01L29/872 ,  H01L29/88 ,  H01L45/00

Abstract: Some embodiments include methods of forming diodes in which a first electrode is formed to have a pedestal extending upwardly from a base. At least one layer is deposited along an undulating topography that extends across the pedestal and base, and a second electrode is formed over the least one layer. The first electrode, at least one layer, and second electrode together form a structure that conducts current between the first and second electrodes when voltage of one polarity is applied to the structure, and that inhibits current flow between the first and second electrodes when voltage having a polarity opposite to said one polarity is applied to the structure. Some embodiments include diodes having a first electrode that contains two or more projections extending upwardly from a base, having at least one layer over the first electrode, and having a second electrode over the at least one layer.

公开(公告)号：US09337210B2

公开(公告)日：2016-05-10

申请号：US13964309

申请日：2013-08-12

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Chandra Mouli ,  Gurtej S. Sandhu

IPC: H01L27/115 ,  H01L21/02 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66 ,  G11C11/22

CPC classification number: H01L27/11597 ,  G11C11/22 ,  H01L21/02568 ,  H01L21/28291 ,  H01L27/11514 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/11582 ,  H01L27/11585 ,  H01L27/1159 ,  H01L29/0649 ,  H01L29/1037 ,  H01L29/24 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/516 ,  H01L29/6684 ,  H01L29/7827 ,  H01L29/78642 ,  H01L29/78681 ,  H01L2029/42388

Abstract: A vertical ferroelectric field effect transistor construction comprises an isolating core. A transition metal dichalcogenide material encircles the isolating core and has a lateral wall thickness of 1 monolayer to 7 monolayers. A ferroelectric gate dielectric material encircles the transition metal dichalcogenide material. Conductive gate material encircles the ferroelectric gate dielectric material. The transition metal dichalcogenide material extends elevationally inward and elevationally outward of the conductive gate material. A conductive contact is directly against a lateral outer sidewall of the transition metal dichalcogenide material that is a) elevationally inward of the conductive gate material, or b) elevationally outward of the conductive gate material. Additional embodiments are disclosed.

Abstract translation: 垂直铁电场效应晶体管结构包括隔离芯。 过渡金属二硫属元素材料环绕隔离芯并具有1个单层至7个单层的侧壁厚度。 铁电栅极电介质材料围绕过渡金属二硫属元素材料。 导电栅极材料围绕铁电栅极电介质材料。 过渡金属二硫属元素材料在导电栅极材料的高度向内和向外向外延伸。 导电接触件直接抵靠过渡金属二硫属化物材料的侧向外侧壁，其是导电栅极材料的顶部向内，或b）导电栅极材料的向外侧。 公开了其他实施例。

公开(公告)号：US09214527B2

公开(公告)日：2015-12-15

申请号：US14543349

申请日：2014-11-17

Applicant: Micron Technology, Inc.

Inventor： Gurtej S. Sandhu ,  Chandra Mouli

IPC: H01L21/28 ,  H01L21/44 ,  H01L29/66 ,  B82Y10/00 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/872 ,  H01L45/00 ,  H01L49/02

Abstract: Some embodiments include methods of forming diodes in which a first electrode is formed to have a pedestal extending upwardly from a base. At least one layer is deposited along an undulating topography that extends across the pedestal and base, and a second electrode is formed over the least one layer. The first electrode, at least one layer, and second electrode together form a structure that conducts current between the first and second electrodes when voltage of one polarity is applied to the structure, and that inhibits current flow between the first and second electrodes when voltage having a polarity opposite to said one polarity is applied to the structure. Some embodiments include diodes having a first electrode that contains two or more projections extending upwardly from a base, having at least one layer over the first electrode, and having a second electrode over the at least one layer.

公开(公告)号：US20150310905A1

公开(公告)日：2015-10-29

申请号：US14260940

申请日：2014-04-24

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Chandra Mouli ,  Durai Vishak Nirmal Ramaswamy ,  F. Daniel Gealy

IPC: G11C11/22 ,  G11C16/10 ,  H01L29/423 ,  H01L29/792 ,  H01L27/115 ,  G11C16/04 ,  H01L29/51

CPC classification number: G11C11/223 ,  G11C11/2275 ,  G11C16/0466 ,  G11C16/10 ,  H01L27/11568 ,  H01L27/1159 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/78391 ,  H01L29/788 ,  H01L29/7923

Abstract: A field effect transistor construction includes a semiconductive channel core. A source/drain region is at opposite ends of the channel core. A gate is proximate a periphery of the channel core. A gate insulator is between the gate and the channel core. The gate insulator has local regions radially there-through that have different capacitance at different circumferential locations relative to the channel core periphery. Additional constructions, and methods, are disclosed.

Abstract translation: 场效应晶体管结构包括半导体沟道芯。 源/漏区位于通道芯的相对端。 门靠近通道核心的外围。 栅极绝缘体在栅极和沟道芯之间。 栅极绝缘体具有径向向内的局部区域，在相对于沟道芯外围的不同圆周位置处具有不同的电容。 公开了附加结构和方法。

公开(公告)号：US09111798B2

公开(公告)日：2015-08-18

申请号：US14447884

申请日：2014-07-31

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Chandra Mouli

IPC: H01L27/115 ,  H01L21/02 ,  H01L21/314 ,  H01L21/84 ,  H01L29/16 ,  H01L29/66 ,  H01L29/78 ,  H01L29/792

CPC classification number: H01L27/11551 ,  H01L21/02529 ,  H01L21/3148 ,  H01L21/84 ,  H01L27/115 ,  H01L27/11568 ,  H01L27/11578 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/66795 ,  H01L29/66833 ,  H01L29/785 ,  H01L29/792

Abstract: A memory includes a first memory cell and a second memory cell formed over the first memory cell. Each of the first memory cell and the second memory cell includes a channel region comprising silicon and carbon, a control gate, and a dielectric stack between the channel region and the control gate. A carbon content of the channel region of the second memory cell is less than a carbon content of the channel region of the first memory cell.

Abstract translation: 存储器包括形成在第一存储单元上的第一存储单元和第二存储单元。 第一存储单元和第二存储单元中的每一个包括在沟道区和控制栅之间包括硅和碳的沟道区，控制栅和电介质叠层。 第二存储单元的沟道区的碳含量小于第一存储单元的沟道区的碳含量。

公开(公告)号：US20150041873A1

公开(公告)日：2015-02-12

申请号：US13964309

申请日：2013-08-12

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Chandra Mouli ,  Gurtej S. Sandhu

IPC: H01L27/115

CPC classification number: H01L27/11597 ,  G11C11/22 ,  H01L21/02568 ,  H01L21/28291 ,  H01L27/11514 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/11582 ,  H01L27/11585 ,  H01L27/1159 ,  H01L29/0649 ,  H01L29/1037 ,  H01L29/24 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/516 ,  H01L29/6684 ,  H01L29/7827 ,  H01L29/78642 ,  H01L29/78681 ,  H01L2029/42388

Abstract: A vertical ferroelectric field effect transistor construction comprises an isolating core. A transition metal dichalcogenide material encircles the isolating core and has a lateral wall thickness of 1 monolayer to 7 monolayers. A ferroelectric gate dielectric material encircles the transition metal dichalcogenide material. Conductive gate material encircles the ferroelectric gate dielectric material. The transition metal dichalcogenide material extends elevationally inward and elevationally outward of the conductive gate material. A conductive contact is directly against a lateral outer sidewall of the transition metal dichalcogenide material that is a) elevationally inward of the conductive gate material, or b) elevationally outward of the conductive gate material. Additional embodiments are disclosed.

Abstract translation: 垂直铁电场效应晶体管结构包括隔离芯。 过渡金属二硫属元素材料环绕隔离芯并具有1个单层至7个单层的侧壁厚度。 铁电栅极电介质材料围绕过渡金属二硫属元素材料。 导电栅极材料围绕铁电栅极电介质材料。 过渡金属二硫属元素材料在导电栅极材料的高度向内和向外向外延伸。 导电接触件直接抵靠过渡金属二硫属化物材料的侧向外侧壁，其是导电栅极材料的顶部向内，或b）导电栅极材料的向外侧。 公开了另外的实施例。

公开(公告)号：US08901625B2

公开(公告)日：2014-12-02

申请号：US14135281

申请日：2013-12-19

Applicant: Micron Technology, Inc.

Inventor： Chandra Mouli

IPC: H01L29/66 ,  H01L29/808 ,  H01L29/10 ,  H01L29/80 ,  H01L29/15

CPC classification number: H01L29/1066 ,  H01L29/155 ,  H01L29/66916 ,  H01L29/802 ,  H01L29/808

Abstract: Devices and methods for providing JFET transistors with improved operating characteristics are provided. Specifically, one or more embodiments of the present invention relate to JFET transistors with a higher diode turn-on voltage. For example, one or more embodiments include a JFET with a PIN gate stack. One or more embodiments also relate to systems and devices in which the improved JFET may be employed, as well as methods of manufacturing the improved JFET.

Abstract translation: 提供了提供具有改进的操作特性的JFET晶体管的器件和方法。 具体地，本发明的一个或多个实施例涉及具有较高二极管导通电压的JFET晶体管。 例如，一个或多个实施例包括具有PIN栅极堆叠的JFET。 一个或多个实施例还涉及其中可以使用改进的JFET的系统和装置，以及制造改进的JFET的方法。

公开(公告)号：US20140110753A1

公开(公告)日：2014-04-24

申请号：US14135281

申请日：2013-12-19

Applicant: Micron Technology, Inc.

Inventor： Chandra Mouli

IPC: H01L29/10 ,  H01L29/80

CPC classification number: H01L29/1066 ,  H01L29/155 ,  H01L29/66916 ,  H01L29/802 ,  H01L29/808

Abstract: Devices and methods for providing JFET transistors with improved operating characteristics are provided. Specifically, one or more embodiments of the present invention relate to JFET transistors with a higher diode turn-on voltage. For example, one or more embodiments include a JFET with a PIN gate stack. One or more embodiments also relate to systems and devices in which the improved JFET may be employed, as well as methods of manufacturing the improved JFET.

Abstract translation: 提供了提供具有改进的操作特性的JFET晶体管的器件和方法。 具体地，本发明的一个或多个实施例涉及具有较高二极管导通电压的JFET晶体管。 例如，一个或多个实施例包括具有PIN栅极堆叠的JFET。 一个或多个实施例还涉及其中可以使用改进的JFET的系统和装置，以及制造改进的JFET的方法。

公开(公告)号：US20130234206A1

公开(公告)日：2013-09-12

申请号：US13872762

申请日：2013-04-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Haitao Liu ,  Jian Li ,  Chandra Mouli

IPC: H01L27/115

CPC classification number: G11C16/14 ,  G11C16/0483 ,  G11C16/10 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/1158 ,  H01L27/11582 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20 ,  H01L29/2003 ,  H01L29/22 ,  H01L29/7926

Abstract: Memory devices are shown that include a body region and a connecting region that is formed from a semiconductor with a lower band gap than the body region. Connecting region configurations can provide increased gate induced drain leakage during an erase operation. Configurations shown can provide a reliable bias to a body region for memory operations such as erasing, and containment of charge in the body region during a boost operation.

Abstract translation: 示出了包括主体区域和由具有比身体区域更低带隙的半导体形成的连接区域的存储器件。 连接区域配置可以在擦除操作期间提供增加的栅极引起的漏极泄漏。 所显示的配置可以提供用于存储器操作的身体区域的可靠偏置，例如在升压操作期间擦除和容纳身体区域中的电荷。