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107 条记录 (耗时 0.02 秒)

    Electrostatic discharge protection
    61.
    发明申请
    Electrostatic discharge protection 有权
    静电放电保护

    公开(公告)号：US20060145261A1

    公开(公告)日：2006-07-06

    申请号：US11324995

    申请日：2006-01-03

    申请人： Harald Gossner

    发明人： Harald Gossner

    IPC分类号： H01L23/62

    CPC分类号： H01L27/0262

    摘要： An electrostatic discharge (“ESD”) protection device, which includes a thyristor circuit, in the ESD case increases a resistance of the ESD protection device in comparison with a non-ESD case, by means of a switch. An ESD protection arrangement may include a ESD protection device to protects circuits with multiple voltage potentials. An ESD protection system may also include an ESD protection arrangement, to which an ESD signal is fed via a bus of the ESD protection system. The ESD protection device and ESD protection arrangement, and thus the ESD protection system, can be provided in a compact semiconductor arrangement.

    摘要翻译： ESD保护装置中包括晶闸管电路的静电放电（“ESD”）保护装置通过开关增加了与非ESD情况相比的ESD保护装置的电阻。 ESD保护装置可以包括用于保护具有多个电压电位的电路的ESD保护装置。 ESD保护系统还可以包括ESD保护装置，ESD信号经由ESD保护系统的总线馈送到ESD保护装置。 ESD保护装置和ESD保护装置以及因此的ESD保护系统可以以紧凑的半导体布置提供。

    ESD protective apparatus for a semiconductor circuit having an ESD protective circuit which makes contact with a substrate or guard ring contact
    62.
    发明申请
    ESD protective apparatus for a semiconductor circuit having an ESD protective circuit which makes contact with a substrate or guard ring contact 审中-公开
    具有与衬底或保护环接触的ESD保护电路的半导体电路的ESD保护装置

    公开(公告)号：US20050179088A1

    公开(公告)日：2005-08-18

    申请号：US11059778

    申请日：2005-02-16

    申请人： Ulrich Glaser ,  Harald Gossner ,  Jens Schneider ,  Martin Streibl ,  Silke Bargstadt-Franke

    发明人： Ulrich Glaser ,  Harald Gossner ,  Jens Schneider ,  Martin Streibl ,  Silke Bargstadt-Franke

    IPC分类号： H01L23/62 ,  H01L27/02

    CPC分类号： H01L27/0266 ,  H01L27/0255

    摘要： An electrostatic discharge (ESD) protective apparatus for a semiconductor circuit has at least one ESD protective element, which is connected between the substrate contact and a ground potential connection, and is electrically connected to the substrate contact. The ESD protective element may be in the form of an ESD protective diode or an ESD protective transistor. It is also possible to connect a resistor or an ESD protective transistor between the substrate contact and the ground potential connection as an ESD protective element, and additionally to connect an ESD protective diode or an ESD protective transistor between the substrate contact and a supply voltage potential connection.

    摘要翻译： 用于半导体电路的静电放电（ESD）保护装置具有至少一个ESD保护元件，其连接在基板触点和地电位连接之间，并且电连接到基板触点。 ESD保护元件可以是ESD保护二极管或ESD保护晶体管的形式。 也可以在基板触点和接地电位连接之间连接一个电阻器或ESD保护晶体管作为ESD保护元件，另外还可以在基板触点和电源电压电位之间连接ESD保护二极管或ESD保护晶体管 连接。

    SRAM memory cell
    64.
    发明授权
    SRAM memory cell 失效
    SRAM存储单元

    公开(公告)号：US6067247A

    公开(公告)日：2000-05-23

    申请号：US47162

    申请日：1998-03-23

    申请人： Harald Gossner ,  Ignaz Eisele ,  Franz Wittmann ,  Rao Ramgopal

    发明人： Harald Gossner ,  Ignaz Eisele ,  Franz Wittmann ,  Rao Ramgopal

    IPC分类号： G11C11/412 ,  G11C11/40 ,  G11C16/04 ,  G11C11/41

    CPC分类号： G11C11/40

    摘要： A three-transistor SRAM memory cell includes a bistable field-effect transistor having a fully depleted floating channel region and a hysteretic gate voltage characteristic curve. The bistable field-effect transistor has a gate to be connected to a first bit line for the purpose of writing to the memory cell and a second channel terminal to be connected to a second bit line for the purpose of reading from the memory cell. The two bit lines can be identical. The connection between the bit lines and the bistable transistor can be effected through first and second respective transistors which are each controlled by a respective word line.

    摘要翻译： 三晶体管SRAM存储单元包括具有完全耗尽的浮动沟道区和迟滞栅极电压特性曲线的双稳态场效应晶体管。 双稳态场效应晶体管具有要连接到第一位线的栅极，用于写入存储器单元，以及要连接到第二位线的第二通道端子，用于从存储单元读取。 两条位线可以相同。 位线和双稳态晶体管之间的连接可以通过第一和第二相应的晶体管实现，这些晶体管各自由相应的字线控制。

    Low voltage ESD clamping using high voltage devices
    67.
    发明授权
    Low voltage ESD clamping using high voltage devices 有权
    使用高压器件的低压ESD钳位

    公开(公告)号：US08654491B2

    公开(公告)日：2014-02-18

    申请号：US13437475

    申请日：2012-04-02

    申请人： Mayank Shrivastava ,  Christian Russ ,  Harald Gossner

    发明人： Mayank Shrivastava ,  Christian Russ ,  Harald Gossner

    IPC分类号： H02H3/22

    CPC分类号： H02H9/046

    摘要： Some embodiments relate to an electrostatic discharge (ESD) protection device. The ESD protection device includes a first electrical path extending between the first and second circuit nodes and including a trigger element. A second electrical path extends between the first and second circuit nodes. The second electrical path includes a shunt element. A switching element is configured to trigger current flow through the shunt element based on both a state of the trigger element and a state of the switching element.

    摘要翻译： 一些实施例涉及静电放电（ESD）保护装置。 ESD保护装置包括在第一和第二电路节点之间延伸并且包括触发元件的第一电路径。 第二电路在第一和第二电路节点之间延伸。 第二电路包括分路元件。 开关元件被配置为基于触发元件的状态和开关元件的状态触发通过分流元件的电流。

    DRAIN EXTENDED MOS DEVICE FOR BULK FINFET TECHNOLOGY
    68.
    发明申请
    DRAIN EXTENDED MOS DEVICE FOR BULK FINFET TECHNOLOGY 有权
    用于大容量FINFET技术的漏极扩展MOS器件

    公开(公告)号：US20140008733A1

    公开(公告)日：2014-01-09

    申请号：US13540762

    申请日：2012-07-03

    申请人： Mayank Shrivastava ,  Harald Gossner

    发明人： Mayank Shrivastava ,  Harald Gossner

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L21/823821 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/66545 ,  H01L29/7835 ,  H01L29/7851

    摘要： Some aspects relate to a FinFET that includes a semiconductor fin disposed over a semiconductor substrate and extending laterally between a source region and a drain region. A shallow trench isolation (STI) region laterally surrounds a lower portion of the semiconductor fin, and an upper portion of the semiconductor fin remains above the STI region. A gate electrode traverses over the semiconductor fin to define a channel region in the semiconductor fin under the conductive gate electrode. A punch-through blocking region can extend between the source region and the channel region in the lower portion of the semiconductor fin. A drain extension region can extend between the drain region and the channel region in the lower portion of the semiconductor fin. Other devices and methods are also disclosed.

    摘要翻译： 一些方面涉及FinFET，其包括设置在半导体衬底上并在源极区域和漏极区域之间横向延伸的半导体鳍片。 浅沟槽隔离（STI）区域横向地围绕半导体鳍片的下部，并且半导体鳍片的上部保持在STI区域上方。 栅电极穿过半导体鳍片，以在导电栅电极下面的半导体鳍片中限定沟道区。 穿通阻挡区域可以在半导体鳍片的下部中的源极区域和沟道区域之间延伸。 漏极延伸区域可以在半导体鳍片的下部中的漏极区域和沟道区域之间延伸。 还公开了其它装置和方法。