公开(公告)号：US08853001B2

公开(公告)日：2014-10-07

申请号：US12959709

申请日：2010-12-03

申请人： Rajendra D. Pendse

发明人： Rajendra D. Pendse

IPC分类号： H01L23/48 ,  H01L23/00 ,  H01L23/498 ,  H01L23/50 ,  H01L21/56 ,  H01L23/31

CPC分类号： H01L24/17 ,  H01L21/56 ,  H01L21/563 ,  H01L21/768 ,  H01L23/3128 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/528 ,  H01L24/03 ,  H01L24/09 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/09133 ,  H01L2224/09135 ,  H01L2224/11 ,  H01L2224/1134 ,  H01L2224/13 ,  H01L2224/13016 ,  H01L2224/13018 ,  H01L2224/13019 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/17133 ,  H01L2224/27013 ,  H01L2224/274 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48157 ,  H01L2224/48158 ,  H01L2224/4816 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81191 ,  H01L2224/812 ,  H01L2224/81385 ,  H01L2224/81801 ,  H01L2224/94 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device has a semiconductor die with a die pad layout. Signal pads in the die pad layout are located primarily near a perimeter of the semiconductor die, and power pads and ground pads are located primarily inboard from the signal pads. The signal pads are arranged in a peripheral row or in a peripheral array generally parallel to an edge of the semiconductor die. Bumps are formed over the signal pads, power pads, and ground pads. The bumps can have a fusible portion and non-fusible portion. Conductive traces with interconnect sites are formed over a substrate. The bumps are wider than the interconnect sites. The bumps are bonded to the interconnect sites so that the bumps cover a top surface and side surfaces of the interconnect sites. An encapsulant is deposited around the bumps between the semiconductor die and substrate.

摘要翻译： 半导体器件具有具有管芯焊盘布局的半导体管芯。 管芯焊盘布局中的信号焊盘主要位于半导体管芯的周边附近，并且电源焊盘和接地焊盘主要位于信号焊盘的内侧。 信号焊盘被布置在大致平行于半导体管芯的边缘的外围行或周边阵列中。 在信号焊盘，电源焊盘和接地焊盘上形成凸起。 凸块可以具有可熔部分和非易熔部分。 具有互连部位的导电迹线形成在衬底上。 凸块比互连部位宽。 凸块与互连部位接合，使得凸块覆盖互连部位的顶表面和侧表面。 围绕半导体管芯和衬底之间的凸块沉积密封剂。

公开(公告)号：US20110074047A1

公开(公告)日：2011-03-31

申请号：US12959709

申请日：2010-12-03

申请人： Rajendra D. Pendse

发明人： Rajendra D. Pendse

IPC分类号： H01L23/485 ,  H01L21/56

CPC分类号： H01L24/17 ,  H01L21/56 ,  H01L21/563 ,  H01L21/768 ,  H01L23/3128 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/528 ,  H01L24/03 ,  H01L24/09 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/09133 ,  H01L2224/09135 ,  H01L2224/11 ,  H01L2224/1134 ,  H01L2224/13 ,  H01L2224/13016 ,  H01L2224/13018 ,  H01L2224/13019 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/17133 ,  H01L2224/27013 ,  H01L2224/274 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48157 ,  H01L2224/48158 ,  H01L2224/4816 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81191 ,  H01L2224/812 ,  H01L2224/81385 ,  H01L2224/81801 ,  H01L2224/94 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device has a semiconductor die with a die pad layout. Signal pads in the die pad layout are located primarily near a perimeter of the semiconductor die, and power pads and ground pads are located primarily inboard from the signal pads. The signal pads are arranged in a peripheral row or in a peripheral array generally parallel to an edge of the semiconductor die. Bumps are formed over the signal pads, power pads, and ground pads. The bumps can have a fusible portion and non-fusible portion. Conductive traces with interconnect sites are formed over a substrate. The bumps are wider than the interconnect sites. The bumps are bonded to the interconnect sites so that the bumps cover a top surface and side surfaces of the interconnect sites. An encapsulant is deposited around the bumps between the semiconductor die and substrate.

摘要翻译： 半导体器件具有具有管芯焊盘布局的半导体管芯。 管芯焊盘布局中的信号焊盘主要位于半导体管芯的周边附近，并且电源焊盘和接地焊盘主要位于信号焊盘的内侧。 信号焊盘被布置在大致平行于半导体管芯的边缘的外围行或周边阵列中。 在信号焊盘，电源焊盘和接地焊盘上形成凸起。 凸块可以具有可熔部分和非易熔部分。 具有互连部位的导电迹线形成在衬底上。 凸块比互连部位宽。 凸块与互连部位接合，使得凸块覆盖互连部位的顶表面和侧表面。 围绕半导体管芯和衬底之间的凸块沉积密封剂。

公开(公告)号：US20150054167A1

公开(公告)日：2015-02-26

申请号：US14503086

申请日：2014-09-30

申请人： STATS ChipPAC, Ltd.

发明人： Rajendra D. Pendse

IPC分类号： H01L23/00 ,  H01L21/56 ,  H01L23/528 ,  H01L21/768

CPC分类号： H01L24/17 ,  H01L21/56 ,  H01L21/563 ,  H01L21/768 ,  H01L23/3128 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/528 ,  H01L24/03 ,  H01L24/09 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/09133 ,  H01L2224/09135 ,  H01L2224/11 ,  H01L2224/1134 ,  H01L2224/13 ,  H01L2224/13016 ,  H01L2224/13018 ,  H01L2224/13019 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/17133 ,  H01L2224/27013 ,  H01L2224/274 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48157 ,  H01L2224/48158 ,  H01L2224/4816 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81191 ,  H01L2224/812 ,  H01L2224/81385 ,  H01L2224/81801 ,  H01L2224/94 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device has a semiconductor die with a die pad layout. Signal pads in the die pad layout are located primarily near a perimeter of the semiconductor die, and power pads and ground pads are located primarily inboard from the signal pads. The signal pads are arranged in a peripheral row or in a peripheral array generally parallel to an edge of the semiconductor die. Bumps are formed over the signal pads, power pads, and ground pads. The bumps can have a fusible portion and non-fusible portion. Conductive traces with interconnect sites are formed over a substrate. The bumps are wider than the interconnect sites. The bumps are bonded to the interconnect sites so that the bumps cover a top surface and side surfaces of the interconnect sites. An encapsulant is deposited around the bumps between the semiconductor die and substrate.

摘要翻译： 半导体器件具有具有管芯焊盘布局的半导体管芯。 管芯焊盘布局中的信号焊盘主要位于半导体管芯的周边附近，并且电源焊盘和接地焊盘主要位于信号焊盘的内侧。 信号焊盘被布置在大致平行于半导体管芯的边缘的外围行或周边阵列中。 在信号焊盘，电源焊盘和接地焊盘上形成凸起。 凸块可以具有可熔部分和非易熔部分。 具有互连部位的导电迹线形成在衬底上。 凸块比互连部位宽。 凸块与互连部位接合，使得凸块覆盖互连部位的顶表面和侧表面。 围绕半导体管芯和衬底之间的凸块沉积密封剂。

公开(公告)号：US09780057B2

公开(公告)日：2017-10-03

申请号：US14503086

申请日：2014-09-30

申请人： STATS ChipPAC, Ltd.

发明人： Rajendra D. Pendse

IPC分类号： H01L23/00 ,  H01L21/56 ,  H01L23/498 ,  H01L23/50 ,  H01L21/768 ,  H01L23/528 ,  H01L23/31

CPC分类号： H01L24/17 ,  H01L21/56 ,  H01L21/563 ,  H01L21/768 ,  H01L23/3128 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/528 ,  H01L24/03 ,  H01L24/09 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/09133 ,  H01L2224/09135 ,  H01L2224/11 ,  H01L2224/1134 ,  H01L2224/13 ,  H01L2224/13016 ,  H01L2224/13018 ,  H01L2224/13019 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/17133 ,  H01L2224/27013 ,  H01L2224/274 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48157 ,  H01L2224/48158 ,  H01L2224/4816 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81191 ,  H01L2224/812 ,  H01L2224/81385 ,  H01L2224/81801 ,  H01L2224/94 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device has a semiconductor die with a die pad layout. Signal pads in the die pad layout are located primarily near a perimeter of the semiconductor die, and power pads and ground pads are located primarily inboard from the signal pads. The signal pads are arranged in a peripheral row or in a peripheral array generally parallel to an edge of the semiconductor die. Bumps are formed over the signal pads, power pads, and ground pads. The bumps can have a fusible portion and non-fusible portion. Conductive traces with interconnect sites are formed over a substrate. The bumps are wider than the interconnect sites. The bumps are bonded to the interconnect sites so that the bumps cover a top surface and side surfaces of the interconnect sites. An encapsulant is deposited around the bumps between the semiconductor die and substrate.

公开(公告)号：US20150084202A1

公开(公告)日：2015-03-26

申请号：US14038248

申请日：2013-09-26

申请人： Georg Seidemann ,  Sven Albers ,  Teodora Ossiander ,  Michael Skinner ,  Hans-Joachim Barth ,  Harald Gossner ,  Reinhard Mahnkoph ,  Christian Mueller ,  Wolfgang Molzer

发明人： Georg Seidemann ,  Sven Albers ,  Teodora Ossiander ,  Michael Skinner ,  Hans-Joachim Barth ,  Harald Gossner ,  Reinhard Mahnkoph ,  Christian Mueller ,  Wolfgang Molzer

IPC分类号： H01L23/00 ,  H01L25/00 ,  H01L25/065

CPC分类号： H01L24/09 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L24/80 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/03444 ,  H01L2224/0346 ,  H01L2224/03602 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05009 ,  H01L2224/05013 ,  H01L2224/05014 ,  H01L2224/05015 ,  H01L2224/05016 ,  H01L2224/05553 ,  H01L2224/05556 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/0558 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/06135 ,  H01L2224/06155 ,  H01L2224/06183 ,  H01L2224/08054 ,  H01L2224/08056 ,  H01L2224/08057 ,  H01L2224/08121 ,  H01L2224/08137 ,  H01L2224/08225 ,  H01L2224/09135 ,  H01L2224/09183 ,  H01L2224/1134 ,  H01L2224/131 ,  H01L2224/16137 ,  H01L2224/48137 ,  H01L2224/80201 ,  H01L2224/80895 ,  H01L2224/81203 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/1434 ,  H01L2224/03 ,  H01L2924/014 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： An apparatus comprises a first integrated circuit (IC) die that includes a top layer, a bottom surface, a sidewall surface extending from a top surface of the top layer to the bottom surface, and at least one multi-surface contact pad, a second IC die including a top layer, a bottom surface, a sidewall surface extending from a top surface of the top layer to the bottom surface, and at least one multi-surface contact pad, wherein the second IC die is arranged adjacent to the first IC die, and includes an electrically conductive bond in contact with at least one of the top surface or the side surface of the multi-surface contact pad of the first IC die and the top surface of the multi-surface contact pad of the second IC die.

摘要翻译： 一种装置包括第一集成电路（IC）芯片，其包括顶层，底表面，从顶层的顶表面延伸到底表面的侧壁表面，以及至少一个多表面接触垫，第二 IC芯片包括顶层，底面，从顶层的顶表面延伸到底表面的侧壁表面，以及至少一个多表面接触焊盘，其中第二IC管芯被布置为与第一IC 并且包括与第一IC管芯的多表面接触焊盘的顶表面或侧表面中的至少一个与第二IC管芯的多表面接触焊盘的顶表面接触的导电接合 。

公开(公告)号：US20190189589A1

公开(公告)日：2019-06-20

申请号：US15986212

申请日：2018-05-22

申请人： SAMSUNG ELECTRO-MECHANICS CO., LTD.

发明人： Ha Yong JUNG ,  Jae Min CHOI ,  Jae Kul LEE ,  Dong Jin KIM ,  Sung Taek WOO ,  Ji Hye SHIM ,  Woon Ha CHOI ,  Han Sang CHO

IPC分类号： H01L25/065 ,  H01L23/538 ,  H01L23/00 ,  H01L25/00 ,  H01L21/48

CPC分类号： H01L25/0652 ,  H01L21/481 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5389 ,  H01L24/09 ,  H01L24/24 ,  H01L24/25 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/50 ,  H01L24/73 ,  H01L25/50 ,  H01L2224/09135 ,  H01L2224/16225 ,  H01L2224/18 ,  H01L2224/2402 ,  H01L2224/24101 ,  H01L2224/24137 ,  H01L2224/24155 ,  H01L2224/25171 ,  H01L2224/32145 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48159 ,  H01L2224/48165 ,  H01L2224/48997 ,  H01L2224/49171 ,  H01L2224/49176 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/73269 ,  H01L2225/06558 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012

摘要： A fan-out semiconductor package includes: a core member having a first through-hole and including first and second wiring layer disposed on different levels; a first semiconductor chip disposed in the first through-hole; a second semiconductor chip disposed on the first semiconductor chip in the first through-hole so that a second inactive surface faces a first inactive surface; conductive wires disposed on the core member and a second active surface and electrically connecting second connection pads and the second wiring layer to each other; an encapsulant covering at least portions of the core member, the first semiconductor chip, the second semiconductor chip, and the conductive wires and filling at least portions of the first through-hole; and a connection member disposed on the core member and a first active surface and electrically connecting first connection pads and the first wiring layer to each other.

公开(公告)号：US09209143B2

公开(公告)日：2015-12-08

申请号：US14038248

申请日：2013-09-26

申请人： Intel IP Corporation

发明人： Georg Seidemann ,  Sven Albers ,  Teodora Ossiander ,  Michael Skinner ,  Hans-Joachim Barth ,  Harald Gossner ,  Reinhard Mahnkopf ,  Christian Mueller ,  Wolfgang Molzer

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC分类号： H01L24/09 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L24/80 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/03444 ,  H01L2224/0346 ,  H01L2224/03602 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05009 ,  H01L2224/05013 ,  H01L2224/05014 ,  H01L2224/05015 ,  H01L2224/05016 ,  H01L2224/05553 ,  H01L2224/05556 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/0558 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/06135 ,  H01L2224/06155 ,  H01L2224/06183 ,  H01L2224/08054 ,  H01L2224/08056 ,  H01L2224/08057 ,  H01L2224/08121 ,  H01L2224/08137 ,  H01L2224/08225 ,  H01L2224/09135 ,  H01L2224/09183 ,  H01L2224/1134 ,  H01L2224/131 ,  H01L2224/16137 ,  H01L2224/48137 ,  H01L2224/80201 ,  H01L2224/80895 ,  H01L2224/81203 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/1434 ,  H01L2224/03 ,  H01L2924/014 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： An apparatus comprises a first integrated circuit (IC) die that includes a top layer, a bottom surface, a sidewall surface extending from a top surface of the top layer to the bottom surface, and at least one multi-surface contact pad, a second IC die including a top layer, a bottom surface, a sidewall surface extending from a top surface of the top layer to the bottom surface, and at least one multi-surface contact pad, wherein the second IC die is arranged adjacent to the first IC die, and includes an electrically conductive bond in contact with at least one of the top surface or the side surface of the multi-surface contact pad of the first IC die and the top surface of the multi-surface contact pad of the second IC die.

摘要翻译： 一种装置包括第一集成电路（IC）芯片，其包括顶层，底表面，从顶层的顶表面延伸到底表面的侧壁表面，以及至少一个多表面接触垫，第二 IC芯片包括顶层，底面，从顶层的顶表面延伸到底表面的侧壁表面，以及至少一个多表面接触焊盘，其中第二IC管芯被布置为与第一IC 并且包括与第一IC管芯的多表面接触焊盘的顶表面或侧表面中的至少一个与第二IC管芯的多表面接触焊盘的顶表面接触的导电接合 。

公开(公告)号：US20120241984A9

公开(公告)日：2012-09-27

申请号：US12959709

申请日：2010-12-03

申请人： Rajendra D. Pendse

发明人： Rajendra D. Pendse

IPC分类号： H01L23/485 ,  H01L21/56

CPC分类号： H01L24/17 ,  H01L21/56 ,  H01L21/563 ,  H01L21/768 ,  H01L23/3128 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/528 ,  H01L24/03 ,  H01L24/09 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/09133 ,  H01L2224/09135 ,  H01L2224/11 ,  H01L2224/1134 ,  H01L2224/13 ,  H01L2224/13016 ,  H01L2224/13018 ,  H01L2224/13019 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/17133 ,  H01L2224/27013 ,  H01L2224/274 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48157 ,  H01L2224/48158 ,  H01L2224/4816 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81191 ,  H01L2224/812 ,  H01L2224/81385 ,  H01L2224/81801 ,  H01L2224/94 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device has a semiconductor die with a die pad layout. Signal pads in the die pad layout are located primarily near a perimeter of the semiconductor die, and power pads and ground pads are located primarily inboard from the signal pads. The signal pads are arranged in a peripheral row or in a peripheral array generally parallel to an edge of the semiconductor die. Bumps are formed over the signal pads, power pads, and ground pads. The bumps can have a fusible portion and non-fusible portion. Conductive traces with interconnect sites are formed over a substrate. The bumps are wider than the interconnect sites. The bumps are bonded to the interconnect sites so that the bumps cover a top surface and side surfaces of the interconnect sites. An encapsulant is deposited around the bumps between the semiconductor die and substrate.

摘要翻译： 半导体器件具有具有管芯焊盘布局的半导体管芯。 管芯焊盘布局中的信号焊盘主要位于半导体管芯的周边附近，并且电源焊盘和接地焊盘主要位于信号焊盘的内侧。 信号焊盘被布置在大致平行于半导体管芯的边缘的外围行或周边阵列中。 在信号焊盘，电源焊盘和接地焊盘上形成凸起。 凸块可以具有可熔部分和非易熔部分。 具有互连部位的导电迹线形成在衬底上。 凸块比互连部位宽。 凸块与互连部位接合，使得凸块覆盖互连部位的顶表面和侧表面。 围绕半导体管芯和衬底之间的凸块沉积密封剂。