公开(公告)号：US11817437B2

公开(公告)日：2023-11-14

申请号：US17516458

申请日：2021-11-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jing-Cheng Lin ,  Po-Hao Tsai

IPC: H01L23/498 ,  H01L25/10 ,  H01L25/11 ,  H01L25/00 ,  H01L21/683 ,  H01L21/02 ,  H01L21/768 ,  H01L23/00 ,  H01L25/065 ,  H01L21/66 ,  H01L21/56 ,  H01L23/427 ,  H01L21/48 ,  H01L23/538 ,  H01L23/31

CPC classification number: H01L25/117 ,  H01L21/02354 ,  H01L21/6835 ,  H01L21/76883 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/03 ,  H01L24/09 ,  H01L24/11 ,  H01L24/14 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L21/486 ,  H01L21/565 ,  H01L21/568 ,  H01L22/14 ,  H01L23/3128 ,  H01L23/427 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/81 ,  H01L24/83 ,  H01L2221/68359 ,  H01L2224/02331 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2224/08111 ,  H01L2224/131 ,  H01L2224/1308 ,  H01L2224/13021 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32013 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49113 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2224/83102 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2225/06586 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/18161 ,  H01L2224/05647 ,  H01L2924/00014 ,  H01L2224/131 ,  H01L2924/014 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2224/13155 ,  H01L2924/00014 ,  H01L2224/13144 ,  H01L2924/00014 ,  H01L2224/13164 ,  H01L2924/00014 ,  H01L2224/83102 ,  H01L2924/00014 ,  H01L2224/2919 ,  H01L2924/0665 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2224/97 ,  H01L2224/81 ,  H01L2224/97 ,  H01L2224/83 ,  H01L2224/97 ,  H01L25/105

Abstract: A method includes forming an under bump metallization (UBM) layer over a dielectric layer, forming a redistribution structure over the UBM layer, disposing a semiconductor device over the redistribution structure, removing a portion of the dielectric layer to form an opening to expose the UBM layer, and forming a conductive bump in the opening such that the conductive bump is coupled to the UBM layer.

公开(公告)号：US11756802B2

公开(公告)日：2023-09-12

申请号：US17815410

申请日：2022-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jing-Cheng Lin ,  Li-Hui Cheng ,  Po-Hao Tsai

IPC: H01L21/56 ,  H01L21/48 ,  H01L21/683 ,  H01L23/367 ,  H01L23/31 ,  H01L23/373 ,  H01L23/42 ,  H01L23/538 ,  H01L23/00 ,  H01L25/11 ,  H01L25/00

CPC classification number: H01L21/566 ,  H01L21/486 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/4871 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3675 ,  H01L23/3736 ,  H01L23/42 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L25/117 ,  H01L25/50 ,  H01L2221/68318 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2221/68381 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/214 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/15311 ,  H01L2924/1815 ,  H01L2924/18162

Abstract: A method includes forming a release film over a carrier, attaching a device over the release film through a die-attach film, encapsulating the device in an encapsulating material, performing a planarization on the encapsulating material to expose the device, detaching the device and the encapsulating material from the carrier, etching the die-attach film to expose a back surface of the device, and applying a thermal conductive material on the back surface of the device.

公开(公告)号：US11637086B2

公开(公告)日：2023-04-25

申请号：US17140791

申请日：2021-01-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Wei Lu ,  Ying-Da Wang ,  Li-Chung Kuo ,  Jing-Cheng Lin

IPC: H01L23/00 ,  H01L23/31 ,  H01L25/065 ,  H01L21/56 ,  H01L21/78

Abstract: A method includes bonding a first and a second package component on a top surface of a third package component, and dispensing a polymer. The polymer includes a first portion in a space between the first and the third package components, a second portion in a space between the second and the third package components, and a third portion in a gap between the first and the second package components. A curing step is then performed on the polymer. After the curing step, the third portion of the polymer is sawed to form a trench between the first and the second package components.

公开(公告)号：US11631654B2

公开(公告)日：2023-04-18

申请号：US17094161

申请日：2020-11-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Wei Lu ,  Ying-Da Wang ,  Li-Chung Kuo ,  Jing-Cheng Lin

IPC: H01L25/065 ,  H01L21/78 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00

Abstract: A method includes bonding a first and a second package component on a top surface of a third package component, and dispensing a polymer. The polymer includes a first portion in a space between the first and the third package components, a second portion in a space between the second and the third package components, and a third portion in a gap between the first and the second package components. A curing step is then performed on the polymer. After the curing step, the third portion of the polymer is sawed to form a trench between the first and the second package components.

公开(公告)号：US11532577B2

公开(公告)日：2022-12-20

申请号：US16989466

申请日：2020-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Ting Shih ,  Nai-Wei Liu ,  Jing-Cheng Lin ,  Cheng-Lin Huang

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L23/31 ,  H01L21/56

Abstract: An embodiment is a method including depositing a first dielectric layer over a molding compound and a chip and patterning a first opening in the first dielectric layer to expose a contact of the chip. A first metallization layer is deposited over the first dielectric layer and in the first opening, where a portion of the first metallization layer in the first opening has a flat top. A second dielectric layer is deposited over the first metallization layer and the first dielectric layer. A second metallization layer is deposited in a second opening in the second dielectric layer, where the second metallization layer does not have a flat top within the second opening.

公开(公告)号：US11527464B2

公开(公告)日：2022-12-13

申请号：US17068310

申请日：2020-10-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jing-Cheng Lin

IPC: H01L23/538 ,  H01L23/498 ,  H01L25/10 ,  H01L23/00 ,  H01L25/03 ,  H01L25/00

Abstract: A method for forming a package structure may comprise applying a die and vias on a carrier having an adhesive layer and forming a molded substrate over the carrier and around the vias, and the ends of the vias and mounts on the die exposed. The vias may be in via chips with one or more dielectric layers separating the vias. The via chips 104 may be formed separately from the carrier. The dielectric layer of the via chips may separate the vias from, and comprise a material different than, the molded substrate. An RDL having RDL contact pads and conductive lines may be formed on the molded substrate. A second structure having at least one die may be mounted on the opposite side of the molded substrate, the die on the second structure in electrical communication with at least one RDL contact pad.

公开(公告)号：US11282793B2

公开(公告)日：2022-03-22

申请号：US16046399

申请日：2018-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih Ting Lin ,  Szu-Wei Lu ,  Jing-Cheng Lin ,  Chen-Hua Yu

IPC: H01L23/538 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/532

Abstract: A method of forming a package assembly includes forming a first dielectric layer over a carrier substrate; forming a conductive through-via over the first dielectric layer; treating the conductive through-via with a first chemical, thereby roughening surfaces of the conductive through-via; and molding a device die and the conductive through-via in a molding material.

公开(公告)号：US20210327778A1

公开(公告)日：2021-10-21

申请号：US17362185

申请日：2021-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Wen-Hsin Wei ,  Chi-Hsi Wu ,  Shang-Yun Hou ,  Jing-Cheng Lin ,  Hsien-Pin Hu ,  Ying-Ching Shih ,  Szu-Wei Lu

IPC: H01L23/31 ,  H01L23/16 ,  H01L21/56 ,  H01L23/00 ,  H01L23/14 ,  H01L21/48 ,  H01L25/03 ,  H01L25/065 ,  H01L23/48 ,  H01L23/498

Abstract: An embodiment is a method including: attaching a first die to a first side of a first component using first electrical connectors, attaching a first side of a second die to first side of the first component using second electrical connectors, attaching a dummy die to the first side of the first component in a scribe line region of the first component, adhering a cover structure to a second side of the second die, and singulating the first component and the dummy die to form a package structure.

公开(公告)号：US11114405B2

公开(公告)日：2021-09-07

申请号：US16725190

申请日：2019-12-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jung-Hua Chang ,  Po-Hao Tsai ,  Jing-Cheng Lin

IPC: H01L21/02 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L21/683 ,  H01L21/56 ,  H01L23/498 ,  H01L23/538

Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a chip structure. The semiconductor package structure includes a first conductive structure over the chip structure. The first conductive structure is electrically connected to the chip structure. The first conductive structure includes a first transition layer over the chip structure; a first conductive layer on the first transition layer; and a second conductive layer over the first conductive layer. The first conductive layer is substantially made of twinned copper. A first average roughness of a first top surface of the second conductive layer is less than a second average roughness of a second top surface of the first conductive layer.

公开(公告)号：US11101252B2

公开(公告)日：2021-08-24

申请号：US16548817

申请日：2019-08-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Ting Lin ,  Chin-Fu Kao ,  Jing-Cheng Lin ,  Li-Hui Cheng ,  Szu-Wei Lu

IPC: H01L23/48 ,  H01L23/52 ,  H01L25/10 ,  H01L25/00 ,  H01L23/538 ,  H01L21/56 ,  H01L21/48

Abstract: A package-on-package structure including a first and second package is provided. The first package includes a semiconductor die, through insulator vias, an insulating encapsulant, conductive terminals and a redistribution layer. The semiconductor die has a die height H1. The plurality of through insulator vias is surrounding the semiconductor die and has a height H2, and H2