公开(公告)号：US08710568B2

公开(公告)日：2014-04-29

申请号：US12289222

申请日：2008-10-23

Applicant: Yoshihiko Ozeki ,  Tetsuo Fujii ,  Kenji Kouno

Inventor： Yoshihiko Ozeki ,  Tetsuo Fujii ,  Kenji Kouno

IPC: H01L27/108 ,  H01L29/94

CPC classification number: H01L29/7395 ,  H01L21/76224 ,  H01L21/84 ,  H01L23/481 ,  H01L25/16 ,  H01L27/0611 ,  H01L27/12 ,  H01L29/0657 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48472 ,  H01L2224/73257 ,  H01L2924/00014 ,  H01L2924/10155 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/19104 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A semiconductor device includes a semiconductor substrate that includes a plurality of section having different thicknesses. The sections include a first section having a first thickness and a second section having a second thickness, the second section is the thinnest section among all the sections, and the first thickness is greater than the second thickness. A plurality of isolation trenches penetrates the semiconductor substrate for defining a plurality of element-forming regions in the first section and the second section. A plurality of elements is located at respective ones of the plurality of element-forming regions. The elements include a double-sided electrode element that includes a pair of electrodes separately disposed on the first surface and the second surface, and the double-sided electrode element is located in the second section.

Abstract translation: 半导体器件包括具有不同厚度的多个部分的半导体衬底。 这些部分包括具有第一厚度的第一部分和具有第二厚度的第二部分，第二部分是所有部分中最薄的部分，并且第一厚度大于第二厚度。 多个隔离沟槽穿过半导体衬底，用于在第一部分和第二部分中限定多个元件形成区域。 多个元件位于多个元件形成区域中的相应元件。 元件包括双面电极元件，其包括分开设置在第一表面和第二表面上的一对电极，并且双面电极元件位于第二部分中。

公开(公告)号：US08154073B2

公开(公告)日：2012-04-10

申请号：US11826206

申请日：2007-07-12

Applicant: Takaaki Aoki ,  Tetsuo Fujii ,  Tomofusa Shiga

Inventor： Takaaki Aoki ,  Tetsuo Fujii ,  Tomofusa Shiga

IPC: H01L29/80

CPC classification number: H01L29/7813 ,  H01L29/0696 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7803 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7828 ,  H01L29/8083

Abstract: A semiconductor device includes: a semiconductor substrate; a vertical type trench gate MOS transistor; a Schottky barrier diode; multiple trenches having a stripe pattern to divide an inner region into first and second separation regions; and a poly silicon film in each trench. The first separation region includes a first conductive type region for providing a source and a second conductive type layer for providing a channel region. The first conductive type region is adjacent to a first trench. The poly silicon film in the first trench is coupled with a gate wiring. A second trench is not adjacent to the first conductive type region. The poly silicon film in the second trench is coupled with a source or gate wiring. The substrate in the second separation region is coupled with the source wiring for providing a Schottky barrier.

Abstract translation: 半导体器件包括：半导体衬底; 垂直型沟槽栅极MOS晶体管; 肖特基势垒二极管; 多个沟槽具有条纹图案以将内部区域分成第一和第二分离区域; 和每个沟槽中的多晶硅膜。 第一分离区域包括用于提供源极的第一导电类型区域和用于提供沟道区域的第二导电类型层。 第一导电类型区域与第一沟槽相邻。 第一沟槽中的多晶硅膜与栅极布线耦合。 第二沟槽不与第一导电类型区域相邻。 第二沟槽中的多晶硅膜与源极或栅极布线耦合。 第二分离区域中的衬底与用于提供肖特基势垒的源极配线耦合。

公开(公告)号：US08035154B2

公开(公告)日：2011-10-11

申请号：US12289799

申请日：2008-11-04

Applicant: Takayoshi Naruse ,  Mitsutaka Katada ,  Tetsuo Fujii

Inventor： Takayoshi Naruse ,  Mitsutaka Katada ,  Tetsuo Fujii

IPC: H01L29/788

CPC classification number: H01L27/115 ,  G11C5/063 ,  G11C16/04 ,  H01L21/84 ,  H01L27/11521 ,  H01L27/1203 ,  H01L29/42324 ,  H01L29/7881

Abstract: A semiconductor device includes a semiconductor substrate, a plurality of memory cells, a plurality of bit lines, and a plurality of source lines. The memory cells are located in the semiconductor substrate. Each of the memory cells includes a trench provided in the semiconductor substrate, an oxide layer disposed on a sidewall of the trench, a tunnel oxide layer disposed at a bottom portion of the trench, a floating gate disposed in the trench so as to be surrounded by the oxide layer and the tunnel oxide layer, and an erasing electrode disposed on an opposing side of the tunnel oxide layer from the floating gate. The bit lines and the source lines are alternately arranged on the memory cells in parallel with each other.

Abstract translation: 半导体器件包括半导体衬底，多个存储单元，多个位线和多个源极线。 存储单元位于半导体衬底中。 每个存储器单元包括设置在半导体衬底中的沟槽，设置在沟槽的侧壁上的氧化物层，设置在沟槽的底部的隧道氧化物层，设置在沟槽中以便被包围的浮置栅极 通过氧化物层和隧道氧化物层，以及擦除电极，设置在隧道氧化物层与浮置栅极相对的一侧。 位线和源极线彼此平行地交替布置在存储器单元上。

公开(公告)号：US07968958B2

公开(公告)日：2011-06-28

申请号：US12213711

申请日：2008-06-24

Applicant: Tetsuo Fujii ,  Kazuhiko Sugiura

Inventor： Tetsuo Fujii ,  Kazuhiko Sugiura

IPC: H01L29/84

CPC classification number: B81B7/007 ,  B81B2207/07 ,  B81B2207/097 ,  B81C2203/0118 ,  G01P15/0802 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/16145 ,  H01L2924/00014

Abstract: A semiconductor device includes: a sensor element having a plate shape with a surface and including a sensor structure disposed in a surface portion of the sensor element; and a plate-shaped cap element bonded to the surface of the sensor element. The cap element has a wiring pattern portion facing the sensor element. The wiring pattern portion connects an outer periphery of the surface of the sensor element and the sensor structure so that the sensor structure is electrically coupled with an external element via the outer periphery. The sensor element does not have a complicated multi-layered structure, so that the sensor element is simplified. Further, the dimensions of the device are reduced.

Abstract translation: 半导体器件包括：传感器元件，其具有表面的板形，并且包括设置在传感器元件的表面部分中的传感器结构; 以及结合到传感器元件的表面的板状盖元件。 盖元件具有面向传感器元件的布线图案部分。 布线图形部分连接传感器元件的表面的外周和传感器结构，使得传感器结构经由外周与外部元件电耦合。 传感器元件不具有复杂的多层结构，因此传感器元件被简化。 此外，装置的尺寸减小。

公开(公告)号：US20110133295A1

公开(公告)日：2011-06-09

申请号：US12902696

申请日：2010-10-12

Applicant: Tetsuo Fujii ,  Masaya Tanaka ,  Keisuke Gotoh

Inventor： Tetsuo Fujii ,  Masaya Tanaka ,  Keisuke Gotoh

IPC: H01L29/84 ,  H01L29/06 ,  H01L21/762 ,  H01L21/50

CPC classification number: H01L21/76898 ,  G01P15/0802 ,  G01P15/125 ,  G01P2015/0877 ,  G01P2015/088 ,  H01L23/481 ,  H01L24/16 ,  H01L24/73 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/16 ,  H01L2224/17181 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/73257 ,  H01L2224/80097 ,  H01L2224/80099 ,  H01L2224/80896 ,  H01L2224/81075 ,  H01L2224/81805 ,  H01L2224/81894 ,  H01L2224/83851 ,  H01L2924/00011 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01056 ,  H01L2924/01058 ,  H01L2924/01072 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/1461 ,  H01L2924/3025 ,  H01L2924/351 ,  H01L2224/29075 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A region divided substrate includes a substrate, a plurality of trenches, a conductive layer, and an insulating member. The substrate has a first surface and a second surface opposed to each other. The trenches penetrate the substrate from the first surface to the second surface and divide the substrate into a plurality of partial regions. The conductive layer is disposed on a sidewall of each of the trenches from a portion adjacent to the first surface to a portion adjacent to the second surface. The conductive layer has an electric conductivity higher than an electric conductivity of the substrate. The insulating member fills each of the trenches through the conductive layer.

Abstract translation: 区域分割衬底包括衬底，多个沟槽，导电层和绝缘构件。 基板具有彼此相对的第一表面和第二表面。 沟槽从第一表面穿过基板到第二表面，并将基板分成多个部分区域。 导电层设置在每个沟槽的侧壁上，从与第一表面相邻的部分到与第二表面相邻的部分。 导电层的导电率高于基板的电导率。 绝缘构件通过导电层填充每个沟槽。

公开(公告)号：US07859091B2

公开(公告)日：2010-12-28

申请号：US12068771

申请日：2008-02-12

Applicant: Tetsuo Fujii ,  Kazuhiko Sugiura

Inventor： Tetsuo Fujii ,  Kazuhiko Sugiura

IPC: H01L23/06

CPC classification number: B81B7/007 ,  H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor device includes: a first substrate made of semiconductor and having first regions, which are insulated from each other and disposed in the first substrate; and a second substrate having electric conductivity and having second regions and insulation trenches. Each insulation trench penetrates the second substrate so that the second regions are insulated from each other. The first substrate provides a base substrate, and the second substrate provides a cap substrate. The second substrate is bonded to the first substrate so that a sealed space is provided between a predetermined surface region of the first substrate and the second substrate. The second regions include an extraction conductive region, which is coupled with a corresponding first region.

Abstract translation: 半导体器件包括：由半导体制成的第一衬底，其具有彼此绝缘并设置在第一衬底中的第一区域; 以及具有导电性并具有第二区域和绝缘沟槽的第二基板。 每个绝缘沟槽穿透第二衬底，使得第二区域彼此绝缘。 第一衬底提供基底，第二衬底提供盖衬底。 第二基板被接合到第一基板，使得在第一基板的预定表面区域和第二基板之间设置密封空间。 第二区域包括与对应的第一区域耦合的引出导电区域。

公开(公告)号：US20100176480A1

公开(公告)日：2010-07-15

申请号：US12654707

申请日：2009-12-29

Applicant: Kouji Senda ,  Satoshi Shiraki ,  Yukihiro Maeda ,  Shinichi Hirose ,  Tetsuo Fujii ,  Takashi Nakano

Inventor： Kouji Senda ,  Satoshi Shiraki ,  Yukihiro Maeda ,  Shinichi Hirose ,  Tetsuo Fujii ,  Takashi Nakano

IPC: H01L27/06 ,  H01L21/78

CPC classification number: H01L21/84 ,  H01L23/3107 ,  H01L23/4951 ,  H01L23/49551 ,  H01L24/27 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73204 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method for manufacturing a semiconductor device includes: preparing a wafer formed of a SOI substrate; forming a circuit portion in a principal surface portion; removing a support substrate of the SOI substrate; fixing an insulation member on a backside of a semiconductor layer so as to be opposite to the circuit portion; dicing the wafer and dividing the wafer into multiple chips; arranging a first conductive member on the insulation member so as to be opposite to a part of the low potential reference circuit, and arranging a second conductive member on the insulation member so as to be opposite to a part of the high potential reference circuit; and coupling the first conductive member with a first part of the low potential reference circuit, and coupling the second conductive member with a second part of the high potential reference circuit.

Abstract translation: 一种制造半导体器件的方法包括：制备由SOI衬底形成的晶片; 在主表面部分形成电路部分; 去除SOI衬底的支撑衬底; 将绝缘构件固定在半导体层的背面以与电路部分相对; 切割晶片并将晶片分成多个芯片; 在所述绝缘构件上设置与所述低电位基准电路的一部分相对的第一导电构件，并且在所述绝缘构件上配置与所述高电位基准电路的一部分相反的第二导电构件; 以及将所述第一导电构件与所述低电位参考电路的第一部分耦合，以及将所述第二导电构件与所述高电位参考电路的第二部分耦合。

公开(公告)号：US07685877B2

公开(公告)日：2010-03-30

申请号：US12215884

申请日：2008-06-30

Applicant: Tetsuo Fujii ,  Masahito Imai

Inventor： Tetsuo Fujii ,  Masahito Imai

IPC: G01P15/125

CPC classification number: B81B7/0006 ,  B81B2201/0235 ,  C07C303/32 ,  C07C303/44 ,  G01C19/56 ,  G01C19/5656 ,  G01C19/5719 ,  G01P15/0802 ,  G01P15/125 ,  G01P2015/0817 ,  G01P2015/0828 ,  Y10T29/49002 ,  Y10T29/49004 ,  C07C309/17

Abstract: A semiconductor mechanical sensor having a new structure in which a S/N ratio is improved. In the central portion of a silicon substrate 1, a recess portion 2 is formed which includes a beam structure. A weight is formed at the tip of the beam, and in the bottom surface of the weight in the bottom surface of the recess portion 2 facing the same, an electrode 5 is formed. An alternating current electric power is applied between the weight portion 4 and the electrode 5 so that static electricity is created and the weight is excited by the static electricity. In an axial direction which is perpendicular to the direction of the excitation of the weight, an electrode 6 is disposed to face one surface of the weight and a wall surface of the substrate which faces the same. A change in a capacitance between the facing electrodes is electrically detected, and therefore, a change in a physical force acting in the same direction is detected.

Abstract translation: 具有S / N比提高的新结构的半导体机械传感器。 在硅衬底1的中心部分，形成包括梁结构的凹部2。 在梁的尖端处形成重物，并且在凹部2的底面中的重物的底面中，重物形成为电极5。 在重量部分4和电极5之间施加交流电力，从而产生静电，并且重量被静电激励。 在与重量的激励方向垂直的轴向方向上，电极6设置为面对重物的一个表面和面向其的基板的壁表面。 对面对电极之间的电容变化进行电检测，因此检测到以相同方向作用的物理力的变化。

公开(公告)号：US07671432B2

公开(公告)日：2010-03-02

申请号：US11709271

申请日：2007-02-22

Applicant: Tetsuo Fujii

Inventor： Tetsuo Fujii

IPC: H01L29/84 ,  H01L25/07 ,  G01P9/04 ,  G01C19/56

CPC classification number: G01P1/023 ,  G01P15/0802 ,  G01P15/125 ,  G01P15/18 ,  G01P2015/0828 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A dynamic quantity sensor includes a sensor chip having a movable portion at one surface side thereof and a silicon layer at another surface side thereof. The movable portion is displaced under application of a dynamic quantity. The silicon layer is separated from the movable portion through an insulator. The dynamic quantity sensor also includes a circuit chip for transmitting/receiving electrical signals to/from the sensor chip. The circuit chip is disposed to confront the one surface of the sensor chip through a gap portion and cover the movable portion. The sensor chip and the circuit chip are bonded to each other around the gap portion so that a bonding portion is formed to substantially surround the gap portion and thereby seal the gap portion.

Abstract translation: 动态量传感器包括在其一个表面侧具有可移动部分的传感器芯片和在其另一表面侧的硅层。 可动部分在施加动态量的情况下移动。 硅层通过绝缘体与可动部分分离。 动态量传感器还包括用于向/从传感器芯片发送/接收电信号的电路芯片。 电路芯片设置成通过间隙部分面对传感器芯片的一个表面并覆盖可动部分。 传感器芯片和电路芯片围绕间隙部分彼此接合，使得接合部分基本上围绕间隙部分，从而密封间隙部分。

公开(公告)号：US20090108288A1

公开(公告)日：2009-04-30

申请号：US12289222

申请日：2008-10-23

Applicant: Yoshihiko Ozeki ,  Tetsuo Fujii ,  Kenji Kouno

Inventor： Yoshihiko Ozeki ,  Tetsuo Fujii ,  Kenji Kouno

IPC: H01L29/739 ,  H01L29/78 ,  H01L21/762

CPC classification number: H01L29/7395 ,  H01L21/76224 ,  H01L21/84 ,  H01L23/481 ,  H01L25/16 ,  H01L27/0611 ,  H01L27/12 ,  H01L29/0657 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48472 ,  H01L2224/73257 ,  H01L2924/00014 ,  H01L2924/10155 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/19104 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A semiconductor device includes a semiconductor substrate that includes a plurality of section having different thicknesses. The sections include a first section having a first thickness and a second section having a second thickness, the second section is the thinnest section among all the sections, and the first thickness is greater than the second thickness. A plurality of isolation trenches penetrates the semiconductor substrate for defining a plurality of element-forming regions in the first section and the second section. A plurality of elements is located at respective ones of the plurality of element-forming regions. The elements include a double-sided electrode element that includes a pair of electrodes separately disposed on the first surface and the second surface, and the double-sided electrode element is located in the second section.

Abstract translation: 半导体器件包括具有不同厚度的多个部分的半导体衬底。 这些部分包括具有第一厚度的第一部分和具有第二厚度的第二部分，第二部分是所有部分中最薄的部分，并且第一厚度大于第二厚度。 多个隔离沟槽穿过半导体衬底，用于在第一部分和第二部分中限定多个元件形成区域。 多个元件位于多个元件形成区域中的相应元件。 元件包括双面电极元件，其包括分开设置在第一表面和第二表面上的一对电极，并且双面电极元件位于第二部分中。