公开(公告)号：US08362521B2

公开(公告)日：2013-01-29

申请号：US12767783

申请日：2010-04-26

申请人： Seiji Nakahata ,  Hideaki Nakahata ,  Koji Uematsu ,  Makoto Kiyama ,  Youichi Nagai ,  Takao Nakamura

发明人： Seiji Nakahata ,  Hideaki Nakahata ,  Koji Uematsu ,  Makoto Kiyama ,  Youichi Nagai ,  Takao Nakamura

IPC分类号： H01L31/102 ,  H01L29/20

CPC分类号： H01L33/007 ,  H01L21/02389 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02645 ,  H01L33/0075 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/12032 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2924/00

摘要： Group III nitride semiconductor crystals of a size appropriate for semiconductor devices and methods for manufacturing the same, Group III nitride semiconductor devices and methods for manufacturing the same, and light-emitting appliances. A method of manufacturing a Group III nitride semiconductor crystal includes a process of growing at least one Group III nitride semiconductor crystal substrate on a starting substrate, a process of growing at least one Group III nitride semiconductor crystal layer on the Group III nitride semiconductor crystal substrate, and a process of separating a Group III nitride semiconductor crystal, constituted by the Group III nitride semiconductor crystal substrate and the Group III nitride semiconductor crystal layer, from the starting substrate, and is characterized in that the Group III nitride semiconductor crystal is 10 μm or more but 600 μm or less in thickness, and is 0.2 mm or more but 50 mm or less in width.

摘要翻译： 尺寸适合于半导体器件的III族氮化物半导体晶体及其制造方法，III族氮化物半导体器件及其制造方法以及发光器具。 制造III族氮化物半导体晶体的方法包括在起始衬底上生长至少一种III族氮化物半导体晶体衬底的工艺，在III族氮化物半导体晶体衬底上生长至少一种III族氮化物半导体晶体层的工艺 以及从起始基板分离由III族氮化物半导体晶体基板和III族氮化物半导体晶体层构成的III族氮化物半导体晶体的工序，其特征在于，所述III族氮化物半导体晶体为10μm 以上且600μm以下，宽度为0.2mm以上且50mm以下。

公开(公告)号：US20120273797A1

公开(公告)日：2012-11-01

申请号：US13531279

申请日：2012-06-22

申请人： Masaya Okada ,  Makoto Kiyama ,  Seiji Yaegashi ,  Ken Nakata

发明人： Masaya Okada ,  Makoto Kiyama ,  Seiji Yaegashi ,  Ken Nakata

IPC分类号： H01L29/20

CPC分类号： H01L29/8725 ,  H01L21/8252 ,  H01L27/0605 ,  H01L27/0727 ,  H01L29/0692 ,  H01L29/2003 ,  H01L29/7786 ,  H01L29/7788 ,  H01L29/7789 ,  H01L29/8128 ,  H01L29/872

摘要： There are provided a semiconductor device that includes a bypass protection unit against surge voltage or the like, achieves good withstand voltage characteristics and low on-resistance (low On-state voltage), has a simple structure, and is used for large-current purpose and a method for producing the semiconductor device.In the present invention, the semiconductor device includes an n+-type GaN substrate 1 having a GaN layer that is in ohmic contact with a supporting substrate, a FET having an n−-type GaN drift layer 2 in a first region R1, and an SBD having an anode electrode in a second region R2, the anode electrode being in Schottky contact with the d−-type GaN drift layer 2. The FET and the SBD are arranged in parallel. A drain electrode D of the FET and a cathode electrode C of the SBD are formed on the back of the n+-type GaN substrate 1.

摘要翻译： 提供了一种具有抗浪涌电压等的旁路保护单元的半导体器件，具有良好的耐压特性和低导通电阻（低导通电压），结构简单，用于大电流目的 以及半导体装置的制造方法。 在本发明中，半导体器件包括具有与支撑衬底欧姆接触的GaN层的n +型GaN衬底1，在第一区域R1中具有n型GaN漂移层2的FET和 SBD在第二区域R2中具有阳极电极，阳极与d型GaN漂移层2肖特基接触.FET和SBD平行布置。 FET的漏电极D和SBD的阴极电极C形成在n +型GaN衬底1的背面。

公开(公告)号：US08110484B1

公开(公告)日：2012-02-07

申请号：US12950686

申请日：2010-11-19

申请人： Fumitaka Sato ,  Seiji Nakahata ,  Makoto Kiyama

发明人： Fumitaka Sato ,  Seiji Nakahata ,  Makoto Kiyama

IPC分类号： H01L21/20 ,  H01L21/36

CPC分类号： H01L21/02395 ,  C30B25/04 ,  C30B29/403 ,  H01L21/02433 ,  H01L21/0254 ,  H01L21/02573 ,  H01L21/02576 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02664

摘要： A method for producing a conductive nitride semiconductor substrate circuit includes the steps of forming, on an underlying substrate, a mask including dot or stripe masking portions having a width or diameter of 10 to 100 μm and arranged at a spacing of 250 to 10,000 μm; growing a nitride semiconductor crystal on the underlying substrate by hydride vapor phase epitaxy (HVPE) at a growth temperature of 1,040° C. to 1,150° C. by supplying a group III source gas, a group V source gas, and a silicon-containing gas in a V/III ratio of 1 to 10; and removing the underlying substrate, thus forming a free-standing conductive nitride semiconductor crystal substrate having a resistivity r of 0.0015 Ωcm≦r≦0.01 Ωcm, a thickness of 100 μm or more, and a radius of bow curvature U of 3.5 m≦U≦8 m.

摘要翻译： 一种导电氮化物半导体衬底电路的制造方法，其特征在于，在下面的基板上形成具有宽度为10〜100μm，宽度为250〜10000μm的点状或条状掩模部的掩模的工序， 通过氢化物气相外延（HVPE）在1,040℃至1150℃的生长温度下在下面的衬底上生长氮化物半导体晶体，通过提供III族源气体，V族源气体和含硅 V / III比为1〜10的气体; 并且除去下面的衬底，从而形成电阻率r为0.0015Ω·cm·cm-1;独立电极;0.01Ω·cm·cm，厚度为100μm以上的独立的导电氮化物半导体晶体衬底，以及弓形曲率U的半径 3.5 m＆nlE; U＆nlE; 8 m。

公开(公告)号：US20110223749A1

公开(公告)日：2011-09-15

申请号：US12913062

申请日：2010-10-27

申请人： Hiromu SHIOMI ,  Yu Saitoh ,  Kazuhide Sumiyoshi ,  Akihiro Hachigo ,  Makoto Kiyama ,  Seiji Nakahata

发明人： Hiromu SHIOMI ,  Yu Saitoh ,  Kazuhide Sumiyoshi ,  Akihiro Hachigo ,  Makoto Kiyama ,  Seiji Nakahata

IPC分类号： H01L21/205 ,  H01L21/3063

CPC分类号： H01L21/0262 ,  C30B25/18 ,  C30B29/403 ,  H01L21/02389 ,  H01L21/02439 ,  H01L21/02458 ,  H01L21/02502 ,  H01L21/0254 ,  H01L21/30617 ,  H01L21/30621 ,  H01L21/7813

摘要： The present method of forming a nitride semiconductor epitaxial layer includes the steps of growing at least one layer of nitride semiconductor epitaxial layer on a nitride semiconductor substrate having a dislocation density lower than or equal to 1×107 cm−2 with a chemical decomposition layer interposed therebetween, the chemical decomposition layer being chemically decomposed at least with either a gas or an electrolytic solution, and decomposing the chemical decomposition layer at least with either the gas or the electrolytic solution at least either during or after the step of growing the nitride semiconductor epitaxial layer, thereby separating the nitride semiconductor epitaxial layer from the nitride semiconductor substrate. A high-quality nitride semiconductor epitaxial layer suffering less damage when separated from the nitride semiconductor substrate is thereby formed.

摘要翻译： 本发明的形成氮化物半导体外延层的方法包括以下步骤：在具有低于或等于1×107cm-2的位错密度的氮化物半导体衬底上生长至少一层氮化物半导体外延层，其中化学分解层插入 其间，化学分解层至少用气体或电解液进行化学分解，并且至少在气体或电解液中的化学分解层至少在生长氮化物半导体外延的步骤期间或之后分解 从而将氮化物半导体外延层与氮化物半导体衬底分离。 由此形成与氮化物半导体基板分离时受损少的高质量氮化物半导体外延层。

公开(公告)号：US20110204381A1

公开(公告)日：2011-08-25

申请号：US13126569

申请日：2010-07-09

申请人： Masaya Okada ,  Makoto Kiyama ,  Seiji Yaegashi ,  Ken Nakata

发明人： Masaya Okada ,  Makoto Kiyama ,  Seiji Yaegashi ,  Ken Nakata

IPC分类号： H01L29/20 ,  H01L21/335

CPC分类号： H01L29/8725 ,  H01L21/8252 ,  H01L27/0605 ,  H01L27/0727 ,  H01L29/0692 ,  H01L29/2003 ,  H01L29/7786 ,  H01L29/7788 ,  H01L29/7789 ,  H01L29/8128 ,  H01L29/872

摘要： There are provided a semiconductor device that includes a bypass protection unit against surge voltage or the like, achieves good withstand voltage characteristics and low on-resistance (low On-state voltage), has a simple structure, and is used for large-current purpose and a method for producing the semiconductor device.In the present invention, the semiconductor device includes an n+-type GaN substrate 1 having a GaN layer that is in ohmic contact with a supporting substrate, a FET having an n−-type GaN drift layer 2 in a first region R1, and an SBD having an anode electrode in a second region R2, the anode electrode being in Schottky contact with the n−-type GaN drift layer 2. The FET and the SBD are arranged in parallel. A drain electrode D of the FET and a cathode electrode C of the SBD are formed on the back of the n+-type GaN substrate 1.

摘要翻译： 提供了一种具有抗浪涌电压等的旁路保护单元的半导体器件，具有良好的耐压特性和低导通电阻（低导通电压），结构简单，用于大电流目的 以及半导体装置的制造方法。 在本发明中，半导体器件包括具有与支撑衬底欧姆接触的GaN层的n +型GaN衬底1，在第一区域R1中具有n型GaN漂移层2的FET和 SBD在第二区域R2中具有阳极电极，阳极与n型GaN漂移层2肖特基接触.FET和SBD平行布置。 FET的漏电极D和SBD的阴极电极C形成在n +型GaN衬底1的背面。

公开(公告)号：US07872285B2

公开(公告)日：2011-01-18

申请号：US11569798

申请日：2006-03-01

申请人： Shin Hashimoto ,  Makoto Kiyama ,  Tatsuya Tanabe ,  Kouhei Miura ,  Takashi Sakurada

发明人： Shin Hashimoto ,  Makoto Kiyama ,  Tatsuya Tanabe ,  Kouhei Miura ,  Takashi Sakurada

IPC分类号： H01L29/66 ,  H01L29/207 ,  H01L29/20

CPC分类号： H01L29/7802 ,  H01L29/0878 ,  H01L29/2003 ,  H01L29/8611 ,  H01L29/872

摘要： Affords epitaxial substrates for vertical gallium nitride semiconductor devices that have a structure in which a gallium nitride film of n-type having a desired low carrier concentration can be provided on a gallium nitride substrate of n type. A gallium nitride epitaxial film (65) is provided on a gallium nitride substrate (63). A layer region (67) is provided in the gallium nitride substrate (63) and the gallium nitride epitaxial film (65). An interface between the gallium nitride substrate (43) and the gallium nitride epitaxial film (65) is positioned in the layer region (67). In the layer region (67), a peak value of donor impurity along an axis from the gallium nitride substrate (63) to the gallium nitride epitaxial film (65) is 1×1018 cm−3 or more. The donor impurity is at least either silicon or germanium.

摘要翻译： 提供具有这样的结构的垂直氮化镓半导体器件的外延衬底，其中可以在n型氮化镓衬底上提供具有期望的低载流子浓度的n型氮化镓膜。 氮化镓外延膜（65）设置在氮化镓衬底（63）上。 在氮化镓衬底（63）和氮化镓外延膜（65）中设置一个层区（67）。 氮化镓衬底（43）和氮化镓外延膜（65）之间的界面位于层区（67）中。 在层区域（67）中，供体杂质从氮化镓衬底（63）到氮化镓外延膜（65）的峰的峰值为1×1018cm-3以上。 供体杂质至少是硅或锗。

公开(公告)号：US20080210959A1

公开(公告)日：2008-09-04

申请号：US11727425

申请日：2007-03-27

申请人： Youichi Nagai ,  Makoto Kiyama ,  Takao Nakamura ,  Takashi Sakurada ,  Katsushi Akita ,  Koji Uematsu ,  Ayako Ikeda ,  Koji Katayama ,  Susumu Yoshimoto

发明人： Youichi Nagai ,  Makoto Kiyama ,  Takao Nakamura ,  Takashi Sakurada ,  Katsushi Akita ,  Koji Uematsu ,  Ayako Ikeda ,  Koji Katayama ,  Susumu Yoshimoto

IPC分类号： H01L33/00

CPC分类号： H01L33/32 ,  H01L33/20 ,  H01L33/382 ,  H01L33/505 ,  H01L33/507 ,  H01L33/58 ,  H01L2224/05573 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2924/00014 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/20752 ,  H01L2924/2076 ,  H01L2224/05599 ,  H01L2924/00011 ,  H01L2224/45099

摘要： In order to provide light emitting devices which have simple constructions and thus can be fabricated easily, and can stably provide high light emission efficiencies for a long time period, a light emitting device includes an n-type nitride semiconductor layer at a first main surface side of a nitride semiconductor substrate, a p-type nitride semiconductor layer placed more distantly from the nitride semiconductor substrate than the n-type nitride semiconductor layer at the first main surface side and a light emitting layer placed between the n-type nitride semiconductor layer and the p-type nitride semiconductor layer at the first main surface side. The nitride semiconductor substrate has a resistivity of 0.5 Ω·cm or less and the p-type nitride semiconductor layer side is down-mounted so that light is emitted from the second main surface of the nitride semiconductor substrate at the opposite side from the first main surface.

摘要翻译： 为了提供具有简单结构并因此可以容易地制造并且可以长期稳定地提供高发光效率的发光器件，发光器件在第一主表面侧包括n型氮化物半导体层 的氮化物半导体衬底，比在第一主表面侧的n型氮化物半导体层更远离氮化物半导体衬底设置的p型氮化物半导体层，以及放置在n型氮化物半导体层和 在第一主表面侧的p型氮化物半导体层。 氮化物半导体衬底的电阻率为0.5Ω·cm以下，p型氮化物半导体层侧被下放，使得从氮化物半导体衬底的第二主表面在与第一主体相反的一侧发射光 表面。

公开(公告)号：US20080128706A1

公开(公告)日：2008-06-05

申请号：US11947752

申请日：2007-11-29

申请人： Shinsuke Fujiwara ,  Takashi Sakurada ,  Makoto Kiyama ,  Yusuke Yoshizumi

发明人： Shinsuke Fujiwara ,  Takashi Sakurada ,  Makoto Kiyama ,  Yusuke Yoshizumi

IPC分类号： H01L29/20 ,  H01L21/205

CPC分类号： H01L29/2003 ,  C30B25/02 ,  C30B29/406 ,  H01L21/02389 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/02516 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02658

摘要： Method of high-yield manufacturing superior semiconductor devices includes: a step of preparing a GaN substrate having a ratio St/S—of collective area (St cm2) of inversion domains in, to total area (S cm2) of the principal face of, the GaN substrate—of no more than 0.5, with the density along the (0001) Ga face, being the substrate principal face, of inversion domains whose surface area where the polarity in the [0001] direction is inverted with respect to the principal domain (matrix) is 1 μm2 or more being D cm−2; and a step of growing on the GaN substrate principal face an at least single-lamina semiconductor layer to form semiconductor devices in which the product Sc×D of the area Sc of the device principal faces, and the density D of the inversion domains is made less than 2.3.

摘要翻译： 高产量制造方法优异的半导体器件包括：制备具有集体面积的比率S / T / S的GaN衬底的步骤， （0001）的浓度，在GaN基板的主面的总面积（S cm 2以上）不大于0.5的情况下， 在[0001]方向上的极性相对于主域（矩阵）反转的表面积为反向畴的Ga面作为衬底主面为1μm以上为D cm 2; 并且在GaN衬底主体上生长至少单层半导体层以形成半导体器件的步骤，其中产品S区域S D的区域S < 器件主面，反型域的密度D小于2.3。

公开(公告)号：US07202509B2

公开(公告)日：2007-04-10

申请号：US10923046

申请日：2004-08-23

申请人： Youichi Nagai ,  Makoto Kiyama ,  Takao Nakamura ,  Takashi Sakurada ,  Katsushi Akita ,  Koji Uematsu ,  Ayako Ikeda ,  Koji Katayama ,  Susumu Yoshimoto

发明人： Youichi Nagai ,  Makoto Kiyama ,  Takao Nakamura ,  Takashi Sakurada ,  Katsushi Akita ,  Koji Uematsu ,  Ayako Ikeda ,  Koji Katayama ,  Susumu Yoshimoto

IPC分类号： H01L33/00

CPC分类号： H01L33/32 ,  H01L33/20 ,  H01L33/382 ,  H01L33/505 ,  H01L33/507 ,  H01L33/58 ,  H01L2224/05573 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2924/00014 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/20752 ,  H01L2924/2076 ,  H01L2224/05599 ,  H01L2924/00011 ,  H01L2224/45099

摘要： In order to provide light emitting devices which have simple constructions and thus can be fabricated easily, and can stably provide high light emission efficiencies for a long time period, a light emitting device includes an n-type nitride semiconductor layer at a first main surface side of a nitride semiconductor substrate, a p-type nitride semiconductor layer placed more distantly from the nitride semiconductor substrate than the n-type nitride semiconductor layer at the first main surface side and a light emitting layer placed between the n-type nitride semiconductor layer and the p-type nitride semiconductor layer at the first main surface side. The nitride semiconductor substrate has a resistivity of 0.5 Ω·cm or less and the p-type nitride semiconductor layer side is down-mounted so that light is emitted from the second main surface of the nitride semiconductor substrate at the opposite side from the first main surface.

摘要翻译： 为了提供具有简单结构并因此可以容易地制造并且可以长期稳定地提供高发光效率的发光器件，发光器件在第一主表面侧包括n型氮化物半导体层 的氮化物半导体衬底，比在第一主表面侧的n型氮化物半导体层更远离氮化物半导体衬底设置的p型氮化物半导体层，以及放置在n型氮化物半导体层和 在第一主表面侧的p型氮化物半导体层。 氮化物半导体衬底的电阻率为0.5Ω·cm以下，p型氮化物半导体层侧被下放，使得从氮化物半导体衬底的第二主表面在与第一主体相反的一侧发射光 表面。

公开(公告)号：US07195937B2

公开(公告)日：2007-03-27

申请号：US10484001

申请日：2003-01-23

申请人： Katsushi Akita ,  Masashi Yamashita ,  Makoto Kiyama

发明人： Katsushi Akita ,  Masashi Yamashita ,  Makoto Kiyama

IPC分类号： H01L21/66 ,  G01R31/26 ,  G01N27/02

CPC分类号： H01L22/14 ,  H01L22/34

摘要： A measurement-facilitating method of measuring the breakdown voltage of a semiconductor epitaxial wafer, and a semiconductor epitaxial wafer whose breakdown voltage is superior are realized. In a method of measuring the breakdown voltage of a semiconductor epitaxial wafer having to do with the present invention, the breakdown voltage between contacts 14 and 18 is measured only through the Schottky contacts, without need for ohmic contacts. Inasmuch as the manufacturing process of forming ohmic contacts is accordingly omitted, the semiconductor epitaxial wafer 10 may be readily used in a breakdown-voltage measurement test. The measurement of the wafer-10 breakdown voltage thus may be readily carried out. Likewise, because the inter-contact breakdown voltage V2 of a wafer 10 can be measured prior to manufacturing a working device from it, unsuitable wafers 10 can be excluded before they are cycled through the working-device fabrication process. Reduction in losses can accordingly be counted upon, in contrast to conventional measuring methods, by which inter-contact breakdown voltage V2 is measured following fabrication of the working devices.

摘要翻译： 实现了测量半导体外延晶片的击穿电压的测量方法和击穿电压优良的半导体外延晶片。 在测量与本发明有关的半导体外延晶片的击穿电压的方法中，触点14和18之间的击穿电压仅通过肖特基触点测量，而不需要欧姆接触。 因此省略了形成欧姆接触的制造工艺，因此半导体外延晶片10可以容易地用于击穿电压测量测试。 因此，可以容易地进行晶片-10击穿电压的测量。 同样，由于可以在从其制造工作装置之前测量晶片10的接触间击穿电压V 2 2，所以不适合的晶片10可以在它们循环通过工作装置制造之前被排除 处理。 因此，与传统的测量方法相比，可以减少损耗，通过这些测量方法，在工作装置制造之后测量接触间击穿电压V 2 2。