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335 条记录 (耗时 0.023 秒)

    Chip package structure and manufacturing method thereof
    65.
    发明授权
    Chip package structure and manufacturing method thereof 有权
    芯片封装结构及其制造方法

    公开(公告)号：US09437529B2

    公开(公告)日：2016-09-06

    申请号：US14490683

    申请日：2014-09-19

    申请人： ChipMOS Technologies Inc.

    发明人： Yu-Tang Pan ,  Shih-Wen Chou

    IPC分类号： H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L23/498 ,  H01L23/31

    CPC分类号： H01L23/49568 ,  H01L21/4828 ,  H01L21/4871 ,  H01L21/4875 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3736 ,  H01L23/49503 ,  H01L23/49524 ,  H01L23/49541 ,  H01L23/49586 ,  H01L23/49861 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/04042 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012

    摘要： A chip package structure includes a lead frame having first and second patterned metal layers and an insulation layer, a chip, and an encapsulant covering the first patterned metal layer and the chip. The first patterned metal layer includes a chip pad with first recesses and bonding pads in the first recesses. A first groove exists between each bonding pad and the chip pad. The second patterned metal layer connecting the first patterned metal layer includes terminal pads and a heat dissipation block thermally coupled to the chip pad. The heat dissipation block includes second recesses where the terminal pads are located and electrically connected to the corresponding bonding pads. A second groove exists between each terminal pad and the heat dissipation block. The insulation layer is located between the bonding pads and the terminal pads. The chip on the chip pad is electrically connected to the bonding pads.

    摘要翻译： 芯片封装结构包括具有第一和第二图案化金属层的引线框架和绝缘层，芯片以及覆盖第一图案化金属层和芯片的密封剂。 第一图案化金属层包括在第一凹部中具有第一凹部和接合焊盘的芯片焊盘。 在每个焊盘和芯片焊盘之间存在第一凹槽。 连接第一图案化金属层的第二图案化金属层包括端子焊盘和热耦合到芯片焊盘的散热块。 散热块包括第二凹部，其中端子焊盘位于并电连接到相应的焊盘。 在每个端子焊盘和散热块之间存在第二凹槽。 绝缘层位于接合焊盘和端子焊盘之间。 芯片焊盘上的芯片电连接到焊盘。

    Semiconductor package structure and manufacturing method thereof
    69.
    发明授权
    Semiconductor package structure and manufacturing method thereof 有权
    半导体封装结构及其制造方法

    公开(公告)号：US09196553B2

    公开(公告)日：2015-11-24

    申请号：US13352346

    申请日：2012-01-18

    申请人： Tsung-Jen Liao ,  Mei-Fang Peng ,  Cheng-Tang Huang

    发明人： Tsung-Jen Liao ,  Mei-Fang Peng ,  Cheng-Tang Huang

    IPC分类号： H01L23/60 ,  H01L23/13 ,  H01L23/498 ,  H01L25/10 ,  H01L21/683

    CPC分类号： H01L23/13 ,  H01L21/6835 ,  H01L23/49816 ,  H01L23/49827 ,  H01L25/105 ,  H01L2221/68345 ,  H01L2221/68363 ,  H01L2224/16 ,  H01L2225/1041 ,  H01L2225/1058

    摘要： A manufacturing method of semiconductor package structure includes: providing a first dielectric layer having multiple through holes; providing a second dielectric layer having multiple conductive vias and a chip-containing opening; laminating the second dielectric layer onto the first dielectric layer; disposing a chip in the chip-containing opening and adhering a rear surface of the chip onto the first dielectric layer exposed by the chip-containing opening; forming a redistribution circuit layer on the second dielectric layer wherein a part of the redistribution circuit layer extends from the second dielectric layer onto an active surface of the chip and the conductive vias so that the chip electrically connects the conductive vias through the partial redistribution circuit layer; forming multiple solder balls on the first dielectric layer wherein the solder balls are in the through holes and electrically connect the chip through the conductive vias and the redistribution circuit layer.

    摘要翻译： 半导体封装结构的制造方法包括：提供具有多个通孔的第一电介质层; 提供具有多个导电通孔和含芯片的开口的第二电介质层; 将第二电介质层层压到第一介电层上; 将芯片设置在含芯片的开口中并将芯片的后表面粘附到由含芯片的开口暴露的第一介质层上; 在所述第二电介质层上形成再分布电路层，其中所述再分布电路层的一部分从所述第二电介质层延伸到所述芯片的有源表面和所述导电通孔，使得所述芯片将所述导电通孔电连接到所述部分再分布电路层 ; 在第一介电层上形成多个焊球，其中焊球位于通孔中，并通过导电通孔和再分布电路层将芯片电连接。

    Chip structure and multi-chip stack package
    70.
    发明授权
    Chip structure and multi-chip stack package 有权
    芯片结构和多芯片堆栈封装

    公开(公告)号：US09018772B2

    公开(公告)日：2015-04-28

    申请号：US13845129

    申请日：2013-03-18

    申请人： ChipMOS Technologies Inc.

    发明人： Tsung-Jen Liao

    IPC分类号： H01L25/04 ,  H01L25/065 ,  H01L25/075 ,  H01L23/538 ,  H01L23/00 ,  H01L23/48

    CPC分类号： H01L23/5386 ,  H01L23/481 ,  H01L24/11 ,  H01L25/043 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/0756 ,  H01L2224/16145 ,  H01L2224/49174 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06565 ,  H01L2924/12042 ,  H01L2924/00

    摘要： A chip structure and a multi-chip stack package are provided. The chip structure includes a chip, at least one interlink plate and a plurality of first connection terminals. The chip has an active surface, a back surface opposite to the active surface and a plurality of side surfaces respectively connected to the active surface and the back surface. The chip includes at least one bond pad disposed on the active surface and at least one joint pad disposed on the back surface. The interlink plate substantially parallel to one of the side surfaces includes a base and a conductive pattern disposed on the base. The conductive pattern is located between the base and the chip. The first connection terminals are disposed between the chip and the interlink plate. The bond pad is electrically connected to the joint pad through the first connection terminals and the conductive pattern.

    摘要翻译： 提供了芯片结构和多芯片堆叠封装。 芯片结构包括芯片，至少一个互连板和多个第一连接端子。 芯片具有活性表面，与活性表面相对的后表面和分别连接到活性表面和后表面的多个侧表面。 芯片包括设置在有源表面上的至少一个接合焊盘和设置在后表面上的至少一个接合焊盘。 基本上平行于一个侧表面的互连板包括基部和设置在基部上的导电图案。 导电图案位于基底和芯片之间。 第一连接端子设置在芯片和互连板之间。 接合焊盘通过第一连接端子和导电图案电连接到接头焊盘。