公开(公告)号：US20180138140A1

公开(公告)日：2018-05-17

申请号：US15867008

申请日：2018-01-10

申请人： Siliconware Precision Industries Co., Ltd.

发明人： Hsin-Ta Lin ,  Ching-Wen Chiang

IPC分类号： H01L23/00 ,  H01L21/48 ,  H01L23/498 ,  H01L23/31

CPC分类号： H01L24/13 ,  H01L21/4846 ,  H01L23/3192 ,  H01L23/49816 ,  H01L23/49894 ,  H01L24/11 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/13016 ,  H01L2224/13025 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2924/2064

摘要： A substrate structure is provided, which includes: a substrate body having a plurality of conductive pads; an insulating layer formed on the substrate body and exposing the conductive pads; a plurality of conductive vias formed in the insulating layer and electrically connected to the conductive pads; a plurality of circuits formed on the conductive vias and in the insulating layer, wherein the circuits are greater in width than the conductive vias; and a plurality of conductive posts formed on the circuits and the insulating layer, wherein each of the conductive posts has a width greater than or equal to that of each of the circuits. The conductive vias, the circuits and the conductive posts are integrally formed. As such, micro-chips or fine-pitch conductive pads can be electrically connected to the substrate structure in a flip-chip manner.

公开(公告)号：US20180130731A1

公开(公告)日：2018-05-10

申请号：US15343270

申请日：2016-11-04

申请人： General Electric Company

发明人： Risto Ilkka Tuominen ,  Arun Virupaksha Gowda

IPC分类号： H01L23/498 ,  H01L23/00 ,  H01L21/48

CPC分类号： H01L23/49838 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/49866 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L25/16 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/12105 ,  H01L2224/291 ,  H01L2224/29139 ,  H01L2224/32225 ,  H01L2224/32227 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/9212 ,  H01L2224/92144 ,  H01L2924/13055 ,  H01L2924/143 ,  H01L2924/1431 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3511 ,  H01L2924/014 ,  H01L2924/00014

摘要： An electronics package includes an insulating substrate, an electrical component coupled to a first surface of the insulating substrate, and a stepped conductor layer formed on a second surface of the insulating substrate, opposite the first surface. The stepped conductor layer includes a first portion that extends into at least one via formed through the insulating substrate to electrically couple with at least one contact pad of the electrical component and a second portion spaced away from the at least one via, the second portion having a thickness greater than the first portion.

公开(公告)号：US09953913B1

公开(公告)日：2018-04-24

申请号：US15375771

申请日：2016-12-12

申请人： General Electric Company

发明人： Arun Virupaksha Gowda ,  Raymond Albert Fillion ,  Paul Alan McConnelee

IPC分类号： H01L23/04 ,  H01L23/498 ,  H01L23/31 ,  H01L23/66 ,  H01L21/48 ,  H01L21/56 ,  H01L23/373 ,  H01L25/07 ,  H01L23/00

CPC分类号： H01L23/49838 ,  H01L21/4846 ,  H01L21/56 ,  H01L23/3121 ,  H01L23/49827 ,  H01L23/4985 ,  H01L23/66 ,  H01L24/05 ,  H01L24/32 ,  H01L25/072 ,  H01L2224/32245 ,  H01L2924/10253 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/19043

摘要： An electronics package includes an insulating substrate, a semiconductor device having a top surface coupled to a first side of the insulating substrate, and a pass-through component coupled to the first side of the insulating substrate. The pass-through component includes an insulating core and at least one through-hole structure comprising a conductive body extending through the thickness of the insulating core. A metallization layer is formed on a second side of the insulating substrate and extends through at least one via in the insulating substrate to electrically couple at least one conductive pad on the top surface of the semiconductor device to the at least one through-hole structure. An insulating material surrounds the semiconductor device and the insulating core of the pass-through component.

公开(公告)号：US20180102299A1

公开(公告)日：2018-04-12

申请号：US15837452

申请日：2017-12-11

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ying-Ju Chen ,  An-Jhih Su ,  Hsien-Wei Chen ,  Der-Chyang Yeh ,  Chi-Hsi Wu ,  Chen-Hua Yu

IPC分类号： H01L23/31 ,  H01L21/56 ,  H01L21/48 ,  H01L23/522 ,  H01L23/538 ,  H01L23/00 ,  H01L23/498

CPC分类号： H01L23/3128 ,  H01L21/4846 ,  H01L21/563 ,  H01L23/49816 ,  H01L23/5226 ,  H01L23/5383 ,  H01L23/5389 ,  H01L24/11 ,  H01L24/14 ,  H01L24/19 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/26145 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/14 ,  H01L2924/19104

摘要： A semiconductor device and method of reducing the risk of underbump metallization poisoning from the application of underfill material is provided. In an embodiment a spacer is located between a first underbump metallization and a second underbump metallization. When an underfill material is dispensed between the first underbump metallization and the second underbump metallization, the spacer prevents the underfill material from creeping towards the second underbump metallization. In another embodiment a passivation layer is used to inhibit the flow of underfill material as the underfill material is being dispensed.

公开(公告)号：US20180090413A1

公开(公告)日：2018-03-29

申请号：US15566385

申请日：2016-04-11

申请人： MITSUBISHI MATERIALS CORPORATION

发明人： Nobuyuki Terasaki ,  Yoshiyuki Nagatomo

IPC分类号： H01L23/373 ,  H01L23/367 ,  H01L23/498 ,  H01L21/48

CPC分类号： H01L23/3735 ,  B23K20/02 ,  B23K20/26 ,  B23K2103/10 ,  B23K2103/12 ,  B23K2103/18 ,  B23K2103/26 ,  C04B37/00 ,  C04B2237/121 ,  C04B2237/128 ,  C04B2237/343 ,  C04B2237/366 ,  C04B2237/368 ,  C04B2237/402 ,  C04B2237/704 ,  C04B2237/706 ,  C04B2237/708 ,  H01L21/4846 ,  H01L21/4882 ,  H01L23/13 ,  H01L23/142 ,  H01L23/367 ,  H01L23/3737 ,  H01L23/40 ,  H01L23/473 ,  H01L23/49838 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/32225 ,  H05K7/20

摘要： A bonded body is provided in which an aluminum alloy member formed from an aluminum alloy, and a metal member formed from copper, nickel, or silver are bonded to each other. The aluminum alloy member is constituted by an aluminum alloy in which a concentration of Si is in a range of 1 mass % to 25 mass %. The aluminum alloy member and the metal member are subjected to solid-phase diffusion bonding. A compound layer, which is formed through diffusion of Al of the aluminum alloy member and a metal element of the metal member, is provided at a bonding interface between the aluminum alloy member and the metal member. A Mg-concentrated layer, in which a concentration of Mg is to 3 mass % or greater, is formed at the inside of the compound layer, and the thickness of the Mg-concentrated layer is in a range of 1 μm to 30 μm.

公开(公告)号：US09929085B2

公开(公告)日：2018-03-27

申请号：US15171320

申请日：2016-06-02

申请人： GLOBALFOUNDRIES INC.

发明人： John A. Fitzsimmons ,  Mukta G. Farooq ,  Anthony K. Stamper

IPC分类号： H01L23/522 ,  H01L23/498 ,  H01L21/48 ,  H01L49/02

CPC分类号： H01L23/5223 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/498 ,  H01L23/49827 ,  H01L23/49894 ,  H01L28/40

摘要： One aspect of the disclosure relates to an interposer. The interposer may include: a first dielectric layer extending from a substrate in a direction away from a front side of the substrate; a back-end-of-the-line (BEOL) region extending from the substrate in a direction away from the back side of the substrate; a deep trench (DT) capacitor within the substrate and extending toward a back side of the substrate, the DT capacitor having a first portion within the substrate and a second portion within the first dielectric layer; and a through silicon via (TSV) adjacent to the DT capacitor and extending through the first dielectric layer, the substrate, and the BEOL region.

公开(公告)号：US20180076090A1

公开(公告)日：2018-03-15

申请号：US15818913

申请日：2017-11-21

申请人： Infineon Technologies Austria AG

发明人： Andreas Voerckel

IPC分类号： H01L21/82 ,  H01L23/00 ,  H01L21/56 ,  H01L21/683 ,  H01L21/768 ,  H01L23/32 ,  H01L21/48

CPC分类号： H01L21/82 ,  H01L21/4846 ,  H01L21/56 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76838 ,  H01L23/32 ,  H01L24/83 ,  H01L2221/68327 ,  H01L2224/32245 ,  H01L2224/83005 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/181 ,  H01L2924/00

摘要： A method for producing a semiconductor device in accordance with various embodiments may include providing a semiconductor workpiece attached to a first carrier; dicing the semiconductor workpiece and the carrier so as to form at least one individual semiconductor chip; mounting the at least one semiconductor chip with a side facing away from the carrier, to an additional carrier.

公开(公告)号：US09917042B2

公开(公告)日：2018-03-13

申请号：US15147099

申请日：2016-05-05

申请人： Invensas Corporation

发明人： Belgacem Haba ,  Sean Moran

IPC分类号： H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L21/78 ,  H01L25/10 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L23/367 ,  H01L25/065 ,  H01L25/16 ,  H01L25/18 ,  H01L23/04 ,  H01L25/00

CPC分类号： H01L23/498 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/56 ,  H01L21/563 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/04 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/3142 ,  H01L23/3675 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/105 ,  H01L25/16 ,  H01L25/18 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/16113 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2225/1058 ,  H01L2924/1427 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19102 ,  H01L2224/81

摘要： A dielectric element has a plurality of contacts at a first surface and a plurality of first traces coupled thereto which extend in directions parallel to the first surface. A circuit structure made of a plurality of dielectric layers and electrically conductive features thereon includes a plurality of bumps at a first surface which face the contacts of the dielectric element and are joined thereto. Circuit structure contacts at a second surface opposite the first surface are electrically coupled with the bumps through second traces on the circuit structure, the circuit structure contacts configured for connection with a plurality of element contacts of each of a plurality of microelectronic elements, wherein the microelectronic elements can be assembled therewith such that element contacts thereof face and are joined with the circuit structure contacts.

公开(公告)号：US20180061817A1

公开(公告)日：2018-03-01

申请号：US15802525

申请日：2017-11-03

申请人： International Business Machines Corporation ,  STMicroelectronics, Inc.

发明人： Lawrence A. Clevenger ,  Carl J. Radens ,  Yiheng Xu ,  John H. Zhang

IPC分类号： H01L25/18 ,  H01L25/065 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00 ,  H01L21/48 ,  H01L23/538

CPC分类号： H01L25/18 ,  H01L21/4846 ,  H01L23/13 ,  H01L23/15 ,  H01L23/3107 ,  H01L23/49827 ,  H01L23/49894 ,  H01L23/5389 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06568 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2225/06593 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/15156 ,  H01L2924/15313 ,  H01L2924/157

摘要： Self-aligned three dimensional vertically stacked chip stacks and processes for forming the same generally include two or more vertically stacked chips supported by a scaffolding structure, the scaffolding structure defined by a first scaffolding trench and at least one additional scaffolding trench, the first scaffolding trench comprising a bottom surface having a width and a sidewall having a height extending from the bottom surface to define a lowermost trench in a scaffolding layer, the at least one additional scaffolding trench overlaying the first scaffolding trench having a sidewall having a height and a width, wherein the width of the at least one scaffolding trench is greater than the first scaffolding trench width to define a first stair between the first scaffolding trench and the at least one additional trench; a first chip secured to the first scaffolding trench having a height less than the first scaffolding trench sidewall height; and at least one additional chip secured to and supported by the first stair, wherein the at least one additional chip is vertically spaced apart from the first chip.

公开(公告)号：US09905437B2

公开(公告)日：2018-02-27

申请号：US14910110

申请日：2014-08-18

申请人： MITSUBISHI MATERIALS CORPORATION

发明人： Nobuyuki Terasaki ,  Yoshiyuki Nagatomo

IPC分类号： B23K1/00 ,  H01L21/48 ,  B23K35/30 ,  C22C9/00 ,  C22C9/02 ,  H01L23/373 ,  B23K35/362 ,  C22C9/06 ,  B23K35/02

CPC分类号： H01L21/4846 ,  B23K1/0016 ,  B23K35/0222 ,  B23K35/0233 ,  B23K35/0238 ,  B23K35/30 ,  B23K35/302 ,  B23K35/362 ,  C04B2237/12 ,  C04B2237/124 ,  C04B2237/32 ,  C04B2237/366 ,  C04B2237/368 ,  C04B2237/40 ,  C04B2237/402 ,  C04B2237/407 ,  C22C9/00 ,  C22C9/02 ,  C22C9/06 ,  H01L23/3735 ,  H01L2224/32225 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of producing a bonded body is disclosed in which a ceramic member made of ceramics and a Cu member made of Cu or a Cu alloy are bonded to each other, the method including: a laminating step of laminating the ceramic member and the Cu member in a state where a Cu—P-based brazing filler material containing 3 mass % to 10 mass % of P and an active metal material are interposed therebetween; and a heating step of heating the ceramic member and the Cu member which are laminated.