公开(公告)号：US20180272693A1

公开(公告)日：2018-09-27

申请号：US15919603

申请日：2018-03-13

Applicant: SEIKO EPSON CORPORATION

Inventor： Katsuhiko HAYASHI

IPC: B41J2/045 ,  H05K1/18 ,  H05K1/11

CPC classification number: B41J2/0457 ,  B41J2/04541 ,  B41J2/04548 ,  B41J2/04581 ,  B41J2/04588 ,  B41J2/04593 ,  B41J2/04596 ,  H01G2/065 ,  H01G4/228 ,  H01G4/30 ,  H05K1/0231 ,  H05K1/112 ,  H05K1/113 ,  H05K1/181 ,  H05K2201/10015 ,  H05K2201/10522 ,  H05K2201/10636

Abstract: The power supply unit includes a circuit substrate including a first layer that is a surface layer being conductive, a first wiring pattern formed of the first layer, a second layer that is conductive, and a second wiring pattern formed of the second layer, and first and second capacitors formed on the first layer. The first capacitor includes a first terminal and a second terminal. The second capacitor includes a third terminal and a fourth terminal. The circuit substrate includes a first electrode connecting the first terminal of the first capacitor to the first wiring pattern, a second electrode connecting the second terminal of the first capacitor to the second wiring pattern, a third electrode connecting the third terminal of the second capacitor to the second wiring pattern, and a fourth electrode connecting the fourth terminal of the second capacitor to the first wiring pattern.

公开(公告)号：US20180266667A1

公开(公告)日：2018-09-20

申请号：US15913080

申请日：2018-03-06

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Shun KUSUDA

IPC: F21V23/02 ,  H05K1/18 ,  H05K1/11 ,  F21V15/01 ,  H05B33/08 ,  F21V17/08

CPC classification number: F21V23/02 ,  F21V3/00 ,  F21V7/041 ,  F21V7/28 ,  F21V15/01 ,  F21V17/08 ,  F21W2131/10 ,  F21Y2115/10 ,  H05B33/0815 ,  H05B37/02 ,  H05K1/0233 ,  H05K1/115 ,  H05K1/181 ,  H05K2201/09027 ,  H05K2201/09063 ,  H05K2201/10015 ,  H05K2201/1003 ,  H05K2201/10106 ,  H05K2201/10166 ,  H05K2201/10522

Abstract: A circuit board includes: an inductor and a control IC which are included in a switching power supply circuit; and a substrate having a first face, a second face on a reverse side of the first face, and an opening in a center portion of the substrate. The inductor is disposed on the first face, the control IC is disposed on the second face, and at least part of the inductor overlaps with at least part of the control IC when viewed from a direction perpendicular to the first face.

公开(公告)号：US10079101B2

公开(公告)日：2018-09-18

申请号：US15054842

申请日：2016-02-26

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Kyo Kwang Lee ,  Jin Kim ,  Young Ghyu Ahn ,  Chang Su Kim

IPC: H01G4/228 ,  H01G4/30 ,  H01G4/012 ,  H01G4/224 ,  H01G4/232 ,  H05K1/18 ,  H05K1/11 ,  H05K1/02 ,  H05K3/34

CPC classification number: H01G4/30 ,  H01G4/012 ,  H01G4/224 ,  H01G4/232 ,  H05K1/0231 ,  H05K1/111 ,  H05K1/181 ,  H05K3/3431 ,  H05K2201/10015

Abstract: A multilayer ceramic capacitor includes a ceramic body having a plurality of dielectric layers stacked therein, and first and second internal electrodes alternately disposed with at least one among the plurality of dielectric layers interposed therebetween. The first internal electrodes include first and second lead portions exposed to a mounting surface of the ceramic body, and disposed to be spaced apart from each other in a length direction of the ceramic body. The second internal electrodes include a third lead portion exposed to the mounting surface of the ceramic body, and disposed between the first and second lead portions in the length direction of the ceramic body.

公开(公告)号：US20180263108A1

公开(公告)日：2018-09-13

申请号：US15870837

申请日：2018-01-12

Applicant: Renesas Electronics Corporation

Inventor： Tatsuaki TSUKUDA

IPC: H05K1/02 ,  H05K1/18 ,  H05K1/11 ,  H03H7/01

CPC classification number: H05K1/0216 ,  H03H7/0138 ,  H05K1/0218 ,  H05K1/023 ,  H05K1/0298 ,  H05K1/116 ,  H05K1/181 ,  H05K2201/0723 ,  H05K2201/09218 ,  H05K2201/093 ,  H05K2201/10015 ,  H05K2201/10022 ,  H05K2201/1003 ,  H05K2201/10151 ,  H05K2201/10689

Abstract: A wiring board of an electronic device includes: a board terminal connected to a semiconductor device (semiconductor component); a wire formed in a first wiring layer and electrically connected to the board terminal; a conductor pattern formed in a second wiring layer and electrically connected to the wire via a via wire; and another conductor pattern formed in a third wiring layer and supplied with a first fixed potential. The conductor pattern and the another conductor pattern face each other with an insulating layer interposed therebetween, and an area of a region where the conductor pattern and the another conductor pattern face each other is larger than an area of the wire.

公开(公告)号：US20180261578A1

公开(公告)日：2018-09-13

申请号：US15975758

申请日：2018-05-09

Applicant: PHOENIX PIONEER TECHNOLOGY CO., LTD.

Inventor： Shih-Ping HSU ,  Chao-Tsung TSENG

IPC: H01L25/065 ,  H05K1/18 ,  H01L21/683 ,  H05K3/46 ,  H01L25/00 ,  H01L23/00 ,  H01L25/16 ,  H01L23/538 ,  H05K3/00 ,  H05K1/16 ,  H05K1/02 ,  H01L23/50 ,  H01L23/498 ,  H01L21/48 ,  H05K3/28 ,  H05K3/34

CPC classification number: H01L25/0657 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/16 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/16112 ,  H01L2224/16113 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2924/15153 ,  H01L2924/15331 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H05K1/0231 ,  H05K1/162 ,  H05K1/183 ,  H05K1/185 ,  H05K3/0032 ,  H05K3/0044 ,  H05K3/284 ,  H05K3/3431 ,  H05K3/4682 ,  H05K3/4697 ,  H05K2201/10 ,  H05K2201/10007 ,  H05K2201/10015 ,  H05K2201/1003 ,  H05K2201/10037 ,  H05K2201/10545 ,  Y10T29/49131 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A method of manufacturing a package structure is provided, including forming a first wiring layer on a carrier board, forming a plurality of first conductors on the first wiring layer, forming a first insulating layer that encapsulates the first wiring layer and the first conductors, forming a second wiring layer on the first insulating layer, forming a plurality of second conductors on the second wiring layer, forming a second insulating layer that encapsulates the second wiring layer and the second conductors, and forming at least an opening on the second insulating layer for at least one electronic component to be disposed therein. Since the first and second insulating layers are formed before the opening, there is no need of stacking or laminating a substrate that already has an opening, and the electronic component will not be laminated and make a displacement. Therefore, the package structure thus manufactured has a high yield rate. The present invention further provides the package structure.

公开(公告)号：US10076036B2

公开(公告)日：2018-09-11

申请号：US15591619

申请日：2017-05-10

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Kyo Kwang Lee ,  Jin Kyung Joo ,  Chang Su Kim ,  Ho Jun Lee

IPC: H05K1/18 ,  H05K1/11 ,  H01G4/232 ,  H01G4/012 ,  H01G4/018 ,  H01G4/30

CPC classification number: H05K1/181 ,  H01G2/06 ,  H01G4/012 ,  H01G4/018 ,  H01G4/232 ,  H01G4/30 ,  H05K1/111 ,  H05K2201/10015

Abstract: A multilayer capacitor includes a capacitor body including dielectric layers and a plurality of first and second internal electrodes alternately disposed with one of the dielectric layers interposed between each pair of adjacent first and second internal electrodes. First and second via electrodes penetrate through the plurality of second internal electrodes to thereby be exposed to a first surface of the capacitor body, and are disposed to be spaced apart from each other. First and second external electrodes are disposed on two side surfaces of the capacitor body and connected to opposing ends of the first internal electrodes, respectively. Third and fourth external electrodes are disposed on the first surface of the capacitor body to be spaced apart from each other, and are connected to end portions of the first and second via electrodes, respectively.

公开(公告)号：US20180249577A1

公开(公告)日：2018-08-30

申请号：US15888422

申请日：2018-02-05

Applicant: TDK CORPORATION

Inventor： Tatsuya FUKUNAGA

IPC: H05K1/18 ,  H01G11/52 ,  H01G11/26 ,  H01G11/74

CPC classification number: H05K1/181 ,  H01G2/06 ,  H01G4/232 ,  H01G4/32 ,  H01G9/008 ,  H01G9/06 ,  H01G9/151 ,  H01G11/26 ,  H01G11/52 ,  H01G11/74 ,  H01G11/76 ,  H01G11/82 ,  H05K1/0231 ,  H05K2201/10015

Abstract: A capacitor includes a package, a first electrode, a second electrode, a first coupling terminal, a second coupling terminal, and a third coupling terminal. The first electrode and the second electrode face each other and spaced apart from each other to avoid mutual contact. The first electrode and the second electrode are each wound in an eddy shape around a rotational axis inside the package. The first coupling terminal is coupled to the first electrode, and has a part that is led out of the package. The second coupling terminal is coupled to the second electrode, and has a part that is led out of the package. The third coupling terminal is coupled to the second electrode, and has a part that is led out of the package.

公开(公告)号：US20180242444A1

公开(公告)日：2018-08-23

申请号：US15900484

申请日：2018-02-20

Applicant: LAPIS Semiconductor Co., Ltd.

Inventor： Kentaro TODA ,  Kenji ARAI ,  Manabu MIYAZAWA ,  Kenichiro NAGATOMO ,  Touru UENO ,  Tsuguto MARUKO ,  Hirofumi OGAWA ,  Tetsuo OOMORI

IPC: H05K1/02 ,  H05K1/11 ,  H05K1/18

CPC classification number: H05K1/0216 ,  H05K1/0231 ,  H05K1/114 ,  H05K1/115 ,  H05K1/181 ,  H05K2201/09227 ,  H05K2201/09236 ,  H05K2201/10015 ,  H05K2201/10689

Abstract: A circuit board device includes: a printed wiring board; an IC chip provided on an obverse surface of the board and having at least one ground terminal; and a wiring pattern, disposed on the board, for providing a ground potential to the ground terminal of the IC chip. The wiring pattern is disposed on a reverse surface of the printed wiring board. The circuit board device has at least one via that is connected to the wiring pattern and passes through the printed wiring board at a position within a region where the IC chip is mounted on the obverse surface of the printed wiring board.

公开(公告)号：US10057988B2

公开(公告)日：2018-08-21

申请号：US15467686

申请日：2017-03-23

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Young Ghyu Ahn ,  Byoung Hwa Lee

IPC: H01G4/228 ,  H05K1/18 ,  H05K1/11 ,  H01G4/30 ,  H01G4/018 ,  H01G4/012 ,  H01G4/248

CPC classification number: H05K1/181 ,  H01G4/012 ,  H01G4/018 ,  H01G4/232 ,  H01G4/248 ,  H01G4/30 ,  H05K1/111 ,  H05K3/3442 ,  H05K2201/10015 ,  H05K2201/10636

Abstract: A multilayer capacitor and a board having the same includes external electrodes and internal electrodes. The external electrodes include connection portions formed on a mounting surface of a capacitor body and band portions formed on side surfaces of the capacitor body, and the internal electrodes include body portions overlapping each other and lead portions extended from the body portions to the mounting surface of the capacitor body, to thereby be connected to the connection portions of the external electrodes. The body portions are formed to be spaced apart from virtual lines connecting distal ends of the connection portions and distal ends of the band portions to each other.

公开(公告)号：US20180228028A1

公开(公告)日：2018-08-09

申请号：US15945913

申请日：2018-04-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Andreas Huber ,  Harald Huels ,  Stefano S. Oggioni ,  Thomas Strach ,  Thomas-Michael Winkel

IPC: H05K1/18 ,  H05K1/02 ,  H05K3/34 ,  H05K3/00 ,  H05K3/18 ,  H05K3/46 ,  H05K1/14 ,  H05K1/11

CPC classification number: H01L23/49838 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06537 ,  H01L2225/06548 ,  H05K1/0219 ,  H05K1/115 ,  H05K1/144 ,  H05K1/181 ,  H05K1/183 ,  H05K3/0097 ,  H05K3/18 ,  H05K3/34 ,  H05K3/4697 ,  H05K2201/049 ,  H05K2201/10015 ,  H05K2201/10106

Abstract: The invention relates to a method for embedding a discrete electronic device in a chip module. The chip module comprises a multilayer substrate which comprises a plurality of electrically conductive layers stacked above each other and an electrically non-conductive layer arranged between each pair of electrically conductive layers. The chip module is configured to receive one or more chips to be mounted onto a top surface thereof. Each electrically conductive layer comprises one or more electrically conductive structures. A recess is provided in a side surface of the chip module. The discrete electronic device is inserted into the recess. A first electrically conductive connection between a first electrical contact of the discrete electronic device and a first electrically conductive structure is established. Further, a second electrically conductive connection between a second electrical contact of the discrete electronic device and a second electrically conductive structure is established.