公开(公告)号：US20240012710A1

公开(公告)日：2024-01-11

申请号：US18213828

申请日：2023-06-24

Applicant: Rambus Inc.

Inventor： Evan Lawrence ERICKSON ,  John Eric LINSTADT

IPC: G06F11/10

CPC classification number: G06F11/10

Abstract: When writing a block (e.g., cache line) of data to a memory, error detection and correction (EDC) information (check) symbols are calculated. The block of data, a first portion of the check symbols, and metadata are all written concurrently at a first address. The remaining portion of the check symbols are written at a second, different from the first, address. When reading the block of data, a first read command accesses the block of data, the first portion of the check symbols, and the metadata from the first address. Only the first portion of the check symbols is used to determine a first number of errors (if any) in the accessed data. If the first number of errors meets a threshold number of errors, a second read command is issued to access the second portion of the check symbols.

公开(公告)号：US20230420010A1

公开(公告)日：2023-12-28

申请号：US18340803

申请日：2023-06-23

Applicant: Rambus Inc.

Inventor： Richard E. Perego ,  Frederick A. Ware

IPC: G11C7/10 ,  G06F13/16 ,  G11C5/06

CPC classification number: G11C7/1072 ,  G06F13/1678 ,  G06F13/1684 ,  G06F13/1694 ,  G11C5/06 ,  G11C7/1045 ,  G11C7/1075

Abstract: A memory system includes a memory controller with a plurality N of memory-controller blocks, each of which conveys independent transaction requests over external request ports. The request ports are coupled, via point-to-point connections, to from one to N memory devices, each of which includes N independently addressable memory blocks. All of the external request ports are connected to respective external request ports on the memory device or devices used in a given configuration. The number of request ports per memory device and the data width of each memory device changes with the number of memory devices such that the ratio of the request-access granularity to the data granularity remains constant irrespective of the number of memory devices.

公开(公告)号：US11854658B2

公开(公告)日：2023-12-26

申请号：US17696818

申请日：2022-03-16

Applicant: Rambus Inc.

Inventor： Christopher Haywood ,  David Wang

IPC: G11C7/10 ,  G06F11/10 ,  G06F11/07 ,  G11C29/52 ,  G11C29/04 ,  G11C5/04

CPC classification number: G11C7/1072 ,  G06F11/073 ,  G06F11/0778 ,  G06F11/0787 ,  G06F11/1044 ,  G06F11/1048 ,  G06F11/1068 ,  G11C7/1006 ,  G06F11/1008 ,  G11C5/04 ,  G11C29/52 ,  G11C2029/0411

Abstract: A method for operating a DRAM device. The method includes receiving in a memory buffer in a first memory module hosted by a computing system, a request for data stored in RAM of the first memory module from a host controller of the computing system. The method includes receiving with the memory buffer, the data associated with a RAM, in response to the request and formatting with the memory buffer, the data into a scrambled data in response to a pseudo-random process. The method includes initiating with the memory buffer, transfer of the scrambled data into an interface device.

公开(公告)号：US20230412213A1

公开(公告)日：2023-12-21

申请号：US18195524

申请日：2023-05-10

Applicant: Rambus Inc.

Inventor： John W. POULTON ,  Frederick A. WARE ,  Carl W. WERNER

IPC: H04B3/56 ,  H04L25/02 ,  G06F13/40 ,  H03F3/24 ,  H04B3/54

CPC classification number: H04B3/56 ,  H04L25/0272 ,  H04B10/50 ,  H03F3/24 ,  H04B3/54 ,  G06F13/4072

Abstract: A single-ended data transmission system transmits a signal having a signal voltage that is referenced to a power supply voltage and that swings above and below the power supply voltage. The power supply voltage is coupled to a power supply rail that also serves as a signal return path. The signal voltage is derived from two signal supply voltages generated by a pair of charge pumps that draw substantially same amount of current from a power supply.

公开(公告)号：US11843372B2

公开(公告)日：2023-12-12

申请号：US17235283

申请日：2021-04-20

Applicant: Rambus Inc.

Inventor： Huy Nguyen

IPC: H03K19/00 ,  H04B1/04 ,  H04L25/02

CPC classification number: H03K19/0005 ,  H04B1/0458 ,  H04L25/0278 ,  H04L25/0298

Abstract: Described are integrated-circuit die with differential receivers, the inputs of which are coupled to external signal pads. Termination legs coupled to the signal pads support multiple termination topologies. These termination legs can support adjustable impedances, capacitances, or both, which may be controlled using an integrated memory.

公开(公告)号：US11842761B2

公开(公告)日：2023-12-12

申请号：US17390370

申请日：2021-07-30

Applicant: Rambus Inc.

Inventor： Thomas Vogelsang ,  John Eric Linstadt ,  Liji Gopalakrishnan

IPC: G06F12/00 ,  G11C11/408 ,  G11C11/4094 ,  G11C11/4091 ,  G06F13/42

CPC classification number: G11C11/4085 ,  G06F13/4282 ,  G11C11/4091 ,  G11C11/4094

Abstract: A dynamic random access memory (DRAM) component (e.g., module or integrated circuit) can be configured to have multiple rows in the same bank open concurrently. The controller of the component divides the address space of the banks into segments based on row address ranges. These row address ranges do not necessarily correspond to row address ranges of the bank's subarrays (a.k.a. memory array tiles—MATs). When a command is sent to open a row, the controller marks a plurality of the segments as blocked. The controller thereby tracks address ranges in a bank where it will not open a second row unless and until the first row is closed. The memory component may store information about which, and how many, segments should be blocked in response to opening a row. This information may be read by the controller during initialization.

公开(公告)号：US20230376412A1

公开(公告)日：2023-11-23

申请号：US18030971

申请日：2021-10-11

Applicant: RAMBUS INC.

Inventor： Evan Lawrence Erickson ,  Christopher Haywood

IPC: G06F12/02

CPC classification number: G06F12/0292 ,  G06F12/023 ,  G06F2212/154

Abstract: An integrated circuit device includes a first memory to support address translation between local addresses and fabric addresses and a processing circuit, operatively coupled to the first memory. The processing circuit allocates, on a dynamic basis as a donor, a portion of first local memory of a local server as first far memory for access for a first remote server, or as a requester receives allocation of second far memory from the first remote server or a second remote server for access by the local server. The processing circuit bridges the access by the first remote server to the allocated portion of first local memory as the first far memory, through the fabric addresses and the address translation supported by the first memory, or bridge the access by the local server to the second far memory, through the address translation supported by the first memory, and the fabric addresses.

公开(公告)号：US11823757B2

公开(公告)日：2023-11-21

申请号：US17000130

申请日：2020-08-21

Applicant: Rambus Inc.

Inventor： Craig Hampel ,  Mark Horowitz

IPC: G11C29/12 ,  G06F12/08 ,  G06F12/0804 ,  G06F13/16 ,  G11C5/04 ,  G11C7/10 ,  G11C29/00 ,  G06F3/06 ,  G06F12/0897 ,  G11C29/32

CPC classification number: G11C29/1201 ,  G06F3/0611 ,  G06F3/0614 ,  G06F3/0647 ,  G06F3/0688 ,  G06F12/08 ,  G06F12/0804 ,  G06F12/0897 ,  G06F13/1684 ,  G11C5/04 ,  G11C7/10 ,  G11C7/1003 ,  G11C29/12 ,  G11C29/12015 ,  G11C29/32 ,  G11C29/76 ,  G06F2212/205 ,  G06F2212/2022 ,  G06F2212/3042 ,  G06F2212/608 ,  G11C2029/3202 ,  Y02D10/00

Abstract: Volatile memory devices may be on a first memory module that is coupled to a memory controller by a first signal path. A nonvolatile memory device may be on a second memory module that is coupled to the first memory module by a second signal path. A memory transaction for the nonvolatile memory device may be transferred from the memory controller to at least one of the volatile memory devices using the first signal path and data associated with the memory transaction is to be written from at least one of the volatile memory devices to the nonvolatile memory device using the second signal path and a control signal. A durability circuit may generate the control signal based on a comparison of a number of write transactions to a particular memory location with a threshold value.

公开(公告)号：US11823734B2

公开(公告)日：2023-11-21

申请号：US17295753

申请日：2019-11-26

Applicant: Rambus Inc.

Inventor： Thomas Vogelsang

IPC: G11C5/14 ,  G11C11/4091 ,  G11C11/4074 ,  G11C11/4094 ,  G11C11/408

CPC classification number: G11C11/4091 ,  G11C11/4074 ,  G11C11/4094 ,  G11C11/4085 ,  G11C2207/002 ,  G11C2207/005

Abstract: A dynamic memory array of a DRAM device is operated using a bitline voltage that is greater than the operating (i.e., switching) voltage of a majority of the digital logic circuitry of the DRAM device. The digital logic circuitry is operated using a supply voltage that is lower than the voltage used to store/retrieve data on the bitlines of the DRAM array. This allows lower voltage swing (and thus lower power) digital logic to be used for a majority of the non-storage array logic on the DRAM device—thus reducing the power consumption of the non-storage array logic which, in turn, reduces the power consumption of the DRAM device as a whole.

公开(公告)号：US20230362041A1

公开(公告)日：2023-11-09

申请号：US18142977

申请日：2023-05-03

Applicant: Rambus Inc.

Inventor： Ehud Nir

IPC: H04L25/03 ,  H04L27/06

CPC classification number: H04L25/03057 ,  H04L27/06 ,  H04L25/4917

Abstract: Technologies for signaling compression inside a partially unrolled decision feedback equalizer (DFE) are described. The signaling compression associated with partially unrolled DFE results in multiplexers selecting a 1-bit output value from one of two 1-bit input values, which are decoding the actual multi-bit candidate levels and transforming the selected 1-bit output value to a multi-bit sliced value by adding to it a pointer value of a pulse-amplitude modulation (PAM) level. The signaling compression reduces the power and area of an N-tap DFE, where N is a positive integer.