公开(公告)号：US07397106B2

公开(公告)日：2008-07-08

申请号：US11299999

申请日：2005-12-12

申请人： Hao-Yi Tsai ,  Chao-Hsiang Yang ,  Shang-Yun Hou ,  Chia-Lun Tsai ,  Shin-Puu Jeng

发明人： Hao-Yi Tsai ,  Chao-Hsiang Yang ,  Shang-Yun Hou ,  Chia-Lun Tsai ,  Shin-Puu Jeng

IPC分类号： H01L23/62

CPC分类号： H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure having an efficient thermal path and a method for forming the same are provided. The semiconductor structure includes a protection ring over a semiconductor substrate and substantially encloses a laser fuse structure. The laser fuse structure includes a laser fuse and a connection structure connecting the fuse to integrated circuits. The protection ring is thermally coupled to the semiconductor substrate by contacts. The semiconductor structure further includes a metal plate conducting heat generated by a laser beam to the protection ring.

摘要翻译： 提供了具有有效的热路径的半导体结构及其形成方法。 半导体结构包括半导体衬底上的保护环，并且基本上包围激光熔丝结构。 激光熔丝结构包括激光熔丝和将熔丝连接到集成电路的连接结构。 保护环通过触点热耦合到半导体衬底。 半导体结构还包括将由激光束产生的热量传导到保护环的金属板。

公开(公告)号：US20080073753A1

公开(公告)日：2008-03-27

申请号：US11525575

申请日：2006-09-22

申请人： Hao-Yi Tsai ,  Chia-Lun Tsai ,  Shang-Yun Hou ,  Shin-Puu Jeng ,  Shih-Hsun Hsu ,  Wei-Ti Hsu ,  Lin-Ko Feng ,  Chun-Jen Chen

发明人： Hao-Yi Tsai ,  Chia-Lun Tsai ,  Shang-Yun Hou ,  Shin-Puu Jeng ,  Shih-Hsun Hsu ,  Wei-Ti Hsu ,  Lin-Ko Feng ,  Chun-Jen Chen

IPC分类号： H01L23/544

CPC分类号： H01L21/78 ,  H01L21/782 ,  H01L21/784 ,  H01L21/786 ,  H01L22/10 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor wafer structure includes a plurality of dies, a first scribe line extending along a first direction, a second scribe line extending along a second direction and intersecting the first scribe line, wherein the first and the second scribe lines have an intersection region. A test line is formed in the scribe line, wherein the test line crosses the intersection region. Test pads are formed in the test line and only outside a free region defined substantially in the intersection region.

摘要翻译： 半导体晶片结构包括多个模具，沿着第一方向延伸的第一划线，沿着第二方向延伸并且与第一划线交叉的第二划线，其中第一划线和第二划线具有交叉区域。 在划线中形成测试线，其中测试线穿过交叉区域。 测试垫形成在测试线中，并且仅在基本上在交叉区域中限定的自由区域的外部。

公开(公告)号：US20080020559A1

公开(公告)日：2008-01-24

申请号：US11458501

申请日：2006-07-19

申请人： Hsien-Wei Chen ,  Anbiarshy Wu ,  Shih-Hsun Hsu ,  Shang-Yun Hou ,  Hsueh-Chung Chen ,  Shin-Puu Jeng

发明人： Hsien-Wei Chen ,  Anbiarshy Wu ,  Shih-Hsun Hsu ,  Shang-Yun Hou ,  Hsueh-Chung Chen ,  Shin-Puu Jeng

IPC分类号： H01L21/44

CPC分类号： H01L21/76895 ,  H01L22/34 ,  H01L23/5226 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/05093 ,  H01L2224/05096 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/14 ,  H01L2924/30105

摘要： An interconnect structure includes at least a first interconnect layer and a second interconnect layer. Each of the first and second interconnect layers has a pad structure and each pad structure has a respective pad density. The pad density of the pad structure of the second interconnect layer is different from the pad density of the pad structure of the first interconnect layer. The pad structures of the first and second interconnect layers are connected to each other.

摘要翻译： 互连结构至少包括第一互连层和第二互连层。 第一和第二互连层中的每一个具有焊盘结构，并且每个焊盘结构具有相应的焊盘密度。 第二互连层的焊盘结构的焊盘密度不同于第一互连层的焊盘结构的焊盘密度。 第一和第二互连层的焊盘结构彼此连接。

公开(公告)号：US08937389B2

公开(公告)日：2015-01-20

申请号：US13569017

申请日：2012-08-07

申请人： Christianto Chih-Ching Liu ,  Shuo-Mao Chen ,  Der-Chyang Yeh ,  Shang-Yun Hou ,  Shin-Puu Jeng

发明人： Christianto Chih-Ching Liu ,  Shuo-Mao Chen ,  Der-Chyang Yeh ,  Shang-Yun Hou ,  Shin-Puu Jeng

IPC分类号： H01L23/48 ,  H01L21/4763 ,  H01L23/522 ,  H01L21/768 ,  H05K1/02

CPC分类号： H01L23/5226 ,  H01L21/76807 ,  H01L23/147 ,  H01L23/49827 ,  H01L23/5223 ,  H01L23/5227 ,  H01L2924/0002 ,  H05K1/0215 ,  H01L2924/00

摘要： Semiconductor devices and methods of manufacture thereof are disclosed. In an embodiment, a method of manufacturing a semiconductor device includes forming a first conductive structure over a workpiece in a first metallization layer, the first conductive structure including a first portion having a first width and a second portion having a second width. The second width is different than the first width. The method includes forming a second conductive structure in a second metallization layer proximate the first metallization layer, and coupling a portion of the second conductive structure to the first portion of the first conductive structure.

摘要翻译： 公开了半导体器件及其制造方法。 在一个实施例中，制造半导体器件的方法包括在第一金属化层中在工件上形成第一导电结构，第一导电结构包括具有第一宽度的第一部分和具有第二宽度的第二部分。 第二宽度与第一宽度不同。 该方法包括在靠近第一金属化层的第二金属化层中形成第二导电结构，以及将第二导电结构的一部分耦合到第一导电结构的第一部分。

公开(公告)号：US08664760B2

公开(公告)日：2014-03-04

申请号：US13343582

申请日：2012-01-04

申请人： Chen-Hua Yu ,  Shin-Puu Jeng ,  Shang-Yun Hou ,  Cheng-Chieh Hsieh ,  Kuo-Ching Hsu ,  Ying-Ching Shih ,  Po-Hao Tsai ,  Chin-Fu Kao ,  Cheng-Lin Huang ,  Jing-Cheng Lin

发明人： Chen-Hua Yu ,  Shin-Puu Jeng ,  Shang-Yun Hou ,  Cheng-Chieh Hsieh ,  Kuo-Ching Hsu ,  Ying-Ching Shih ,  Po-Hao Tsai ,  Chin-Fu Kao ,  Cheng-Lin Huang ,  Jing-Cheng Lin

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/11 ,  H01L23/147 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/04 ,  H01L25/50 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05073 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05184 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05686 ,  H01L2224/10145 ,  H01L2224/10156 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/1182 ,  H01L2224/11831 ,  H01L2224/13017 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13565 ,  H01L2224/13578 ,  H01L2224/13686 ,  H01L2224/16058 ,  H01L2224/16145 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/3651 ,  H01L2924/3841 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/01047 ,  H01L2924/049 ,  H01L2924/053 ,  H01L2924/00

摘要： A device includes a top dielectric layer having a top surface. A metal pillar has a portion over the top surface of the top dielectric layer. A non-wetting layer is formed on a sidewall of the metal pillar, wherein the non-wetting layer is not wettable to the molten solder. A solder region is disposed over and electrically coupled to the metal pillar.

公开(公告)号：US20140015106A1

公开(公告)日：2014-01-16

申请号：US13546218

申请日：2012-07-11

申请人： Cheng-Chieh Hsieh ,  Way Lee Cheng ,  Shang-Yun Hou ,  Shin-Puu Jeng

发明人： Cheng-Chieh Hsieh ,  Way Lee Cheng ,  Shang-Yun Hou ,  Shin-Puu Jeng

IPC分类号： H01L23/34

CPC分类号： H01L23/427 ,  H01L21/563 ,  H01L23/3675 ,  H01L23/3677 ,  H01L23/562 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06565 ,  H01L2225/06589

摘要： One or more heat pipes are utilized along with a substrate in order to provide heat dissipation through the substrate for heat that can build up at an interface between the substrate and one or more semiconductor chips in a package. In an embodiment the heat pipe may be positioned on a side of the substrate opposite the semiconductor chip and through-substrate vias may be utilized to dissipate heat through the substrate. In an alternative embodiment, the heat pipe may be positioned on a same side of the substrate as the semiconductor chip and may be thermally connected to the one or more semiconductor chips.

摘要翻译： 一个或多个热管与衬底一起使用，以便提供通过衬底的热量，其可以在衬底和封装中的一个或多个半导体芯片之间的界面处积聚。 在一个实施例中，热管可以位于与半导体芯片相对的一侧的衬底上，并且通孔衬底可以用于通过衬底散热。 在替代实施例中，热管可以位于与半导体芯片相同的衬底侧上，并且可以热连接到一个或多个半导体芯片。

公开(公告)号：US08610285B2

公开(公告)日：2013-12-17

申请号：US13298046

申请日：2011-11-16

申请人： Chen-Hua Yu ,  Shin-Puu Jeng ,  Shang-Yun Hou ,  Kuo-Ching Hsu ,  Cheng-Chieh Hsieh ,  Ying-Ching Shih ,  Po-Hao Tsai ,  Cheng-Lin Huang ,  Jing-Cheng Lin

发明人： Chen-Hua Yu ,  Shin-Puu Jeng ,  Shang-Yun Hou ,  Kuo-Ching Hsu ,  Cheng-Chieh Hsieh ,  Ying-Ching Shih ,  Po-Hao Tsai ,  Cheng-Lin Huang ,  Jing-Cheng Lin

IPC分类号： H01L23/498 ,  H01L21/768 ,  H01L23/48 ,  H01L29/40

CPC分类号： H01L24/11 ,  H01L23/147 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/04 ,  H01L25/50 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05073 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05184 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05686 ,  H01L2224/10145 ,  H01L2224/10156 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/1182 ,  H01L2224/11831 ,  H01L2224/13017 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13565 ,  H01L2224/13578 ,  H01L2224/13686 ,  H01L2224/16058 ,  H01L2224/16145 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/3651 ,  H01L2924/3841 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/01047 ,  H01L2924/049 ,  H01L2924/053 ,  H01L2924/00

摘要： A package component is free from active devices therein. The package component includes a substrate, a through-via in the substrate, a top dielectric layer over the substrate, and a metal pillar having a top surface over a top surface of the top dielectric layer. The metal pillar is electrically coupled to the through-via. A diffusion barrier is over the top surface of the metal pillar. A solder cap is disposed over the diffusion barrier.

摘要翻译： 封装组件不含其中的有源器件。 封装部件包括衬底，衬底中的通孔，衬底上的顶部电介质层，以及在顶部电介质层的顶表面上方具有顶表面的金属柱。 金属柱电连接到通孔。 扩散阻挡层在金属支柱的上表面之上。 焊料帽设置在扩散阻挡层上。

公开(公告)号：US20130049220A1

公开(公告)日：2013-02-28

申请号：US13302653

申请日：2011-11-22

申请人： Cheng-Chieh Hsieh ,  Hung-An Teng ,  Shang-Yun Hou ,  Shin-Puu Jeng

发明人： Cheng-Chieh Hsieh ,  Hung-An Teng ,  Shang-Yun Hou ,  Shin-Puu Jeng

IPC分类号： H01L23/48

CPC分类号： H01L23/562 ,  H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

摘要： Keep out zones (KOZ) are formed for a through silicon via (TSV). A device can be placed outside a first KOZ of a TSV determined by a first performance threshold so that a stress impact caused by the TSV to the device is less than a first performance threshold while the first KOZ contains only those points at which a stress impact caused by the TSV is larger than or equal to the first performance threshold. A second KOZ for the TSV can be similarly formed by a second performance threshold. A plurality of TSVs can be placed in a direction that the KOZ of the TSV has smallest radius to a center of the TSV, which may be in a crystal orientation [010] or [100]. A plurality of TSV stress plug can be formed at the boundary of the overall KOZ of the plurality of TSVs.

公开(公告)号：US20110210444A1

公开(公告)日：2011-09-01

申请号：US12813212

申请日：2010-06-10

申请人： Shin-Puu Jeng ,  Kim Hong Chen ,  Shang-Yun Hou ,  Chao-Wen Shih ,  Cheng-Chieh Hsieh ,  Chen-Hua Yu

发明人： Shin-Puu Jeng ,  Kim Hong Chen ,  Shang-Yun Hou ,  Chao-Wen Shih ,  Cheng-Chieh Hsieh ,  Chen-Hua Yu

IPC分类号： H01L23/538 ,  H01L21/60 ,  H01L23/488

CPC分类号： H01L25/50 ,  H01L23/13 ,  H01L23/3677 ,  H01L23/42 ,  H01L23/49827 ,  H01L23/49833 ,  H01L24/16 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00

摘要： A 3D semiconductor package using an interposer is provided. In an embodiment, an interposer is provided having a first die electrically coupled to a first side of the interposer and a second die electrically coupled to a second side of the interposer. The interposer is electrically coupled to an underlying substrate, such as a packaging substrate, a high-density interconnect, a printed circuit board, or the like. The substrate has a cavity such that the second die is positioned within the cavity. The use of a cavity may allow smaller conductive bumps to be used, thereby allowing a higher number of conductive bumps to be used. A heat sink may be placed within the cavity to aid in the dissipation of the heat from the second die.

摘要翻译： 提供了使用插入器的3D半导体封装。 在一个实施例中，提供了具有电耦合到插入器的第一侧的第一管芯的插入器和电耦合到插入件的第二侧的第二管芯。 插入器电耦合到诸如封装衬底，高密度互连，印刷电路板等的下面的衬底。 衬底具有腔，使得第二管芯位于腔内。 使用空腔可以允许使用更小的导电凸块，从而允许使用更多数量的导电凸块。 散热器可以放置在空腔内以帮助从第二模具散热。

公开(公告)号：US20110127648A1

公开(公告)日：2011-06-02

申请号：US13023151

申请日：2011-02-08

申请人： Hsien-Wei Chen ,  Yu-Wen Liu ,  Jyh-Cherng Sheu ,  Hao-Yi Tsai ,  Shin-Puu Jeng ,  Chen-Hua Yu ,  Shang-Yun Hou

发明人： Hsien-Wei Chen ,  Yu-Wen Liu ,  Jyh-Cherng Sheu ,  Hao-Yi Tsai ,  Shin-Puu Jeng ,  Chen-Hua Yu ,  Shang-Yun Hou

IPC分类号： H01L23/544 ,  H01L23/34

CPC分类号： H01L23/3677 ,  B23K26/364 ,  B23K26/40 ,  B23K2103/172 ,  H01L21/78 ,  H01L22/34 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit structure includes a first chip including a first edge; and a second chip having a second edge facing the first edge. A scribe line is between and adjoining the first edge and the second edge. A heat spreader includes a portion in the scribe line, wherein the heat spreader includes a plurality of vias and a plurality of metal lines. The portion of the heat spreader in the scribe line has a second length at least close to, or greater than, a first length of the first edge.

摘要翻译： 集成电路结构包括：第一芯片，包括第一边缘; 以及具有面向第一边缘的第二边缘的第二芯片。 划线在第一边缘和第二边缘之间并相邻。 散热器包括划线中的一部分，其中散热器包括多个通孔和多个金属线。 散热器在划线中的部分具有至少接近或大于第一边缘的第一长度的第二长度。