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123 条记录 (耗时 0.027 秒)

    Threshold voltage tailoring of the corner of a MOSFET device
    71.
    发明授权
    Threshold voltage tailoring of the corner of a MOSFET device 失效
    MOSFET器件角的阈值电压调整

    公开(公告)号：US5994202A

    公开(公告)日：1999-11-30

    申请号：US788065

    申请日：1997-01-23

    申请人： Jeffrey Peter Gambino ,  Gary Bela Bronner ,  Jack Allan Mandelman ,  Larry Alan Nesbit

    发明人： Jeffrey Peter Gambino ,  Gary Bela Bronner ,  Jack Allan Mandelman ,  Larry Alan Nesbit

    IPC分类号： H01L29/78 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/76

    CPC分类号： H01L21/823412 ,  H01L21/76229 ,  H01L21/76237

    摘要： A semiconductor MOSFET device is formed on a silicon substrate which includes trenches filled with Shallow Trench Isolation dielectric trench fill structures and extending above the surface of the substrate. The trench fill structures have protruding sidewalls with channel regions in the substrate having corner regions adjacent to the trench fill structures. The channel regions are between and adjacent to the STI trench fill structures doped with one concentration of dopant in the centers of the channel regions with a higher concentration of dopant in the corner regions. The dopant concentration differential provides a substantially equal concentration of electrons in the centers and at the corner regions of the channel regions.

    摘要翻译： 半导体MOSFET器件形成在硅衬底上，该硅衬底包括填充有浅沟槽隔离电介质沟槽填充结构并在衬底表面上方延伸的沟槽。 沟槽填充结构具有突出的侧壁，其中衬底中的通道区域具有与沟槽填充结构相邻的拐角区域。 沟道区域在与沟槽区域的中心掺杂一个浓度的掺杂剂的STI沟槽填充结构之间并相邻，在拐角区域具有较高浓度的掺杂剂。 掺杂剂浓度差在通道区域的中心和拐角区域提供基本相等的电子浓度。

    Conductor structure including manganese oxide capping layer
    75.
    发明授权
    Conductor structure including manganese oxide capping layer 有权
    导体结构包括氧化锰覆盖层

    公开(公告)号：US08236683B2

    公开(公告)日：2012-08-07

    申请号：US13016340

    申请日：2011-01-28

    申请人： Jeffrey Peter Gambino ,  Stephen Ellinwood Luce

    发明人： Jeffrey Peter Gambino ,  Stephen Ellinwood Luce

    IPC分类号： H01L21/4763

    CPC分类号： H01L23/53238 ,  H01L21/76834 ,  H01L21/76864 ,  H01L21/76871 ,  H01L21/76883 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A microelectronic structure includes a dielectric layer located over a substrate. The dielectric layer is separated from a copper containing conductor layer by an oxidation barrier layer. The microelectronic structure also includes a manganese oxide layer located aligned upon a portion of the copper containing conductor layer not adjoining the oxidation barrier layer. A method for fabricating the microelectronic structure includes sequentially forming and sequentially planarizing within an aperture within a dielectric layer an oxidation barrier layer, a manganese containing layer (or alternatively a mobile and oxidizable material layer) and finally, a planarized copper containing conductor layer (or alternatively a base material layer comprising a material less mobile and oxidizable than the mobile and oxidizable material layer) to completely fill the aperture. The manganese layer and the planarized copper containing conductor layer are then thermally oxidized to form a manganese oxide layer self aligned to a portion of the copper containing conductor layer not adjoining the oxidation barrier layer.

    摘要翻译： 微电子结构包括位于衬底上的电介质层。 通过氧化阻挡层将电介质层与含铜导体层分离。 微电子结构还包括一个位于未包含氧化阻挡层的含铜导体层的一部分上的氧化锰层。 一种用于制造微电子结构的方法包括在电介质层内的孔内依次形成并依次平面化氧化阻挡层，含锰层（或者可移动和可氧化的材料层），最后是平坦化的含铜导体层（或 可选地，基材层包含比移动和可氧化材料层更不易流动和可氧化的材料）以完全填充孔。 然后将锰层和平坦化的含铜导体层热氧化以形成与不与氧化阻挡层相邻的含铜导体层的一部分自对准的氧化锰层。

    Deep trench semiconductor structure and method
    78.
    发明授权
    Deep trench semiconductor structure and method 有权
    深沟槽半导体结构及方法

    公开(公告)号：US08017995B2

    公开(公告)日：2011-09-13

    申请号：US11942756

    申请日：2007-11-20

    申请人： Jeffrey Peter Gambino ,  Benjamin Thomas Voegeli ,  Steven Howard Voldman ,  Michael Joseph Zierak

    发明人： Jeffrey Peter Gambino ,  Benjamin Thomas Voegeli ,  Steven Howard Voldman ,  Michael Joseph Zierak

    IPC分类号： H01L31/119 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

    CPC分类号： H01L21/823437 ,  H01L21/823828 ,  H01L29/1037 ,  H01L29/4236 ,  H01L29/66621 ,  H01L29/66787

    摘要： An electrical structure and method of forming. The electrical structure includes a semiconductor substrate comprising a deep trench, an oxide liner layer is formed over an exterior surface of the deep trench, and a field effect transistor (FET) formed within the semiconductor substrate. The first FET includes a source structure, a drain structure, and a gate structure. The gate structure includes a gate contact connected to a polysilicon fill structure. The polysilicon fill structure is formed over the oxide liner layer and within the deep trench. The polysilicon fill structure is configured to flow current laterally across the polysilicon fill structure such that the current will flow parallel to a top surface of the semiconductor substrate.

    摘要翻译： 一种电气结构和成型方法。 电结构包括半导体衬底，其包括深沟槽，在深沟槽的外表面上形成氧化物衬层，以及形成在半导体衬底内的场效应晶体管（FET）。 第一FET包括源极结构，漏极结构和栅极结构。 栅极结构包括连接到多晶硅填充结构的栅极触点。 多晶硅填充结构形成在氧化物衬垫层之上和深沟槽内。 多晶硅填充结构被配置为横向跨越多晶硅填充结构流动电流，使得电流平行于半导体衬底的顶表面流动。