公开(公告)号：US08080631B2

公开(公告)日：2011-12-20

申请号：US11782191

申请日：2007-07-24

申请人： Yasuharu Yamada ,  Jun Sakai

发明人： Yasuharu Yamada ,  Jun Sakai

IPC分类号： C08G73/10

CPC分类号： C08G77/455 ,  C08G73/106 ,  C08G83/005

摘要： It is an object of the present invention to provide a siloxane-modified hyperbranched polyimide which has more excellent electric properties (low dielectric property), gas permeability, mechanical properties (low modulus), surface properties (adhesiveness) and the like while maintaining thermal stability, mechanical strength, chemical resistance and processability and the like intrinsic to polyimide and which may be variously functionalized and can be utilized advantageously in industrial applications. A siloxane structure represented by the following structural formula (1) is introduced into a three-dimensional structured hyperbranched polyimide molecule. (wherein R1 represents a hydrocarbon group having from 1 to 6 carbon atoms, and n indicates an integer of from 1 to 50).

摘要翻译： 本发明的目的是提供一种硅氧烷改性的超支化聚酰亚胺，其具有更好的电性能（低介电性能），透气性，机械性能（低模量），表面性质（粘合性）等，同时保持热稳定性 ，机械强度，耐化学性和加工性等等，并且可以进行各种功能化并且可以有利地用于工业应用中。 将由以下结构式（1）表示的硅氧烷结构引入三维结构超支化聚酰亚胺分子中。 （其中R1表示碳原子数为1〜6的烃基，n表示1〜50的整数）。

公开(公告)号：US08004085B2

公开(公告)日：2011-08-23

申请号：US12593824

申请日：2008-02-13

申请人： Shintaro Yamamichi ,  Katsumi Kikuchi ,  Jun Sakai ,  Hikaru Kouta

发明人： Shintaro Yamamichi ,  Katsumi Kikuchi ,  Jun Sakai ,  Hikaru Kouta

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L27/10 ,  H01L29/73 ,  H01L29/74

CPC分类号： H01L23/5283 ,  H01L23/3171 ,  H01L23/5286 ,  H01L24/14 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/01047 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05099

摘要： A semiconductor device has an element interconnection 2, a top-layer element interconnection 4, a super-connect interconnection 10 and a bump 7. The element interconnection 2 is provided on a semiconductor substrate 1 through a plurality of insulating layers 50. The top-layer element interconnection 4 is formed above the element interconnection 2 by using a substantially equivalent process equipment. The super-connect interconnection 10 is provided on the top-layer element interconnection 4 through a super-connect insulating layer 9 having a thickness five or more times larger than that of the insulating layer 5, and has a thickness three or more times larger than that of each the element interconnection 2 and the top-layer element interconnection 4. The bump 7 is formed on the super-connect interconnection 10. The top-layer element interconnection 4 has a signal pad 4s, a power source pad 4v and a ground pad 4g. An area of the signal pad 4s is smaller than each area of the power source pad 4v and the ground pad 4g.

摘要翻译： 半导体器件具有元件互连2，顶层元件互连4，超连接互连10和凸块7.元件互连2通过多个绝缘层50设置在半导体衬底1上。 层元件互连4通过使用基本相同的处理设备形成在元件互连2上方。 超连接互连10通过具有比绝缘层5的厚度大五倍以上的厚度的超连接绝缘层9设置在顶层元件布线4上，并且具有比绝缘层5的厚度大三倍以上的厚度 元件互连2和顶层元件互连4中的每一个。凸块7形成在超连接互连10上。顶层元件互连4具有信号焊盘4s，电源焊盘4v和接地 垫4g。 信号焊盘4s的面积比电源焊盘4v和接地焊盘4g的面积小。

公开(公告)号：US20110079422A1

公开(公告)日：2011-04-07

申请号：US12994774

申请日：2008-05-26

申请人： Taras Kushita ,  Jun Sakai ,  Hikaru Kouta

发明人： Taras Kushita ,  Jun Sakai ,  Hikaru Kouta

IPC分类号： H05K1/11

CPC分类号： H05K1/0245 ,  H05K1/0251 ,  H05K1/116 ,  H05K3/429 ,  H05K2201/09309 ,  H05K2201/09636 ,  H05K2201/09718

摘要： A multilayer substrate is provided with a conductor plane region in which a plurality of conductor planes are disposed; a clearance region disposed adjacent to the conductor plane region so that the plurality of conductor planes are excluded from the clearance region. A plurality of signal vias are disposed through the clearance region so that the plurality of signal vias are isolated from the plurality of conductor planes. A conductor post is connected to one of the plurality of conductor planes and disposed between two of the signal vias in the clearance region.

摘要翻译： 多层基板设置有布置有多个导体平面的导体平面区域; 与所述导体平面区域相邻设置的间隙区域，以使所述多个导体平面从所述间隙区域排除。 多个信号通孔设置穿过间隙区域，使得多个信号通孔与多个导体平面隔离。 导体柱连接到多个导体平面中的一个并且设置在间隙区域中的两个信号通孔之间。

公开(公告)号：US20100117228A1

公开(公告)日：2010-05-13

申请号：US12593824

申请日：2008-02-13

申请人： Shintaro Yamamichi ,  Katsumi Kikuchi ,  Jun Sakai ,  Hikaru Kouta

发明人： Shintaro Yamamichi ,  Katsumi Kikuchi ,  Jun Sakai ,  Hikaru Kouta

IPC分类号： H01L23/52 ,  H01L23/48

CPC分类号： H01L23/5283 ,  H01L23/3171 ,  H01L23/5286 ,  H01L24/14 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/01047 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05099

摘要： A semiconductor device has an element interconnection 2, a top-layer element interconnection 4, a super-connect interconnection 10 and a bump 7. The element interconnection 2 is provided on a semiconductor substrate 1 through a plurality of insulating layers 50. The top-layer element interconnection 4 is formed above the element interconnection 2 by using a substantially equivalent process equipment. The super-connect interconnection 10 is provided on the top-layer element interconnection 4 through a super-connect insulating layer 9 having a thickness five or more times larger than that of the insulating layer 5, and has a thickness three or more times larger than that of each the element interconnection 2 and the top-layer element interconnection 4. The bump 7 is formed on the super-connect interconnection 10. The top-layer element interconnection 4 has a signal pad 4s, a power source pad 4v and a ground pad 4g. An area of the signal pad 4s is smaller than each area of the power source pad 4v and the ground pad 4g.

摘要翻译： 半导体器件具有元件互连2，顶层元件互连4，超连接互连10和凸块7.元件互连2通过多个绝缘层50设置在半导体衬底1上。 层元件互连4通过使用基本相同的处理设备形成在元件互连2上方。 超连接互连10通过具有比绝缘层5的厚度大五倍以上的厚度的超连接绝缘层9设置在顶层元件布线4上，并且具有比绝缘层5的厚度大三倍以上的厚度 元件互连2和顶层元件互连4中的每一个。凸块7形成在超连接互连10上。顶层元件互连4具有信号焊盘4s，电源焊盘4v和接地 垫4g。 信号焊盘4s的面积比电源焊盘4v和接地焊盘4g的面积小。

公开(公告)号：US20060103004A1

公开(公告)日：2006-05-18

申请号：US11274182

申请日：2005-11-16

申请人： Jun Sakai ,  Hirobumi Inoue ,  Kazuhiro Motonaga

发明人： Jun Sakai ,  Hirobumi Inoue ,  Kazuhiro Motonaga

IPC分类号： H01L23/12

CPC分类号： H05K1/0218 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/50 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2924/15173 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0219 ,  H05K1/0231 ,  H05K1/0298 ,  H05K1/112 ,  H05K2201/0715 ,  H01L2224/0401

摘要： It is to provide a wiring board for a semiconductor integrated circuit package, which exhibits an excellent signal property and a high effect for decreasing the switching noise at the time of mounting an LSI of an area-array structure. In a multilayer wiring board for a package, which comprises, on a wiring layer of an LSI chip mount surface, a ground pad, a power supply pad, and a signal pad for mounting LSI chip, and a ground plane that extends around a group of those pads, the ground pad disposed on the inner side, among the above-described pads, is connected to the ground plane that surrounds the pad group through a connecting wiring.

摘要翻译： 提供一种用于半导体集成电路封装的布线板，其具有优异的信号特性和用于降低安装区域阵列结构的LSI时的开关噪声的高效果。 在一种用于封装的多层布线板中，其包括在LSI芯片安装表面的布线层上的接地焊盘，电源焊盘和用于安装LSI芯片的信号焊盘以及围绕一组延伸的接地平面 在这些焊盘中，设置在上述焊盘中的内侧的接地焊盘通过连接布线连接到围绕焊盘组的接地平面。

公开(公告)号：US06848320B2

公开(公告)日：2005-02-01

申请号：US10446789

申请日：2003-05-29

申请人： Hisakazu Miyajima ,  Masao Arakawa ,  Akira Yabuta ,  Jun Sakai

发明人： Hisakazu Miyajima ,  Masao Arakawa ,  Akira Yabuta ,  Jun Sakai

IPC分类号： B60J7/057 ,  B81B3/00 ,  B82B1/00 ,  G01L9/00 ,  G01P15/12 ,  H01L29/84 ,  G01L1/14 ,  G01L9/04

CPC分类号： G01P15/123 ,  B81B3/0021 ,  B81B3/0086 ,  B81B2201/0235 ,  B81B2201/0257 ,  B81B2201/0264 ,  B81B2203/0118 ,  B81B2203/0127 ,  G01L9/0055 ,  G01P2015/0828 ,  Y10S977/956

摘要： A mechanical deformation amount sensor includes a sensor structure which is formed by a semiconductor substrate or an insulating substrate and integrally includes a deformation portion deformable, when a physical quantity to be detected is applied to the sensor structure, due to the physical quantity and a support portion for supporting the deformation portion, a carbon nanotube resistance element which is provided on the deformation portion so as to be mechanically deformed in response to deformation of the deformation portion and a wiring pattern which is formed in a pattern on the sensor structure so as to be connected to the carbon nanotube resistance element. By applying a voltage to the carbon nanotube resistance element via the wiring pattern, a change of electrical conductivity of the carbon nanotube resistance element upon mechanical deformation of the carbon nanotube resistance element is fetched as an electrical signal.

摘要翻译： 机械变形量传感器包括由半导体衬底或绝缘衬底形成的传感器结构，并且当由于物理量和支撑体而将待检测物理量应用于传感器结构时，整体地包括可变形部分 用于支撑变形部分的部分，碳纳米管电阻元件，其设置在变形部分上，以便响应于变形部分的变形而机械变形，以及在传感器结构上以图案形成的布线图案，以便 连接到碳纳米管电阻元件。 通过经由布线图案向碳纳米管电阻元件施加电压，碳纳米管电阻元件在碳纳米管电阻元件的机械变形时的电导率的变化被取出作为电信号。

公开(公告)号：US5967110A

公开(公告)日：1999-10-19

申请号：US65277

申请日：1998-04-23

申请人： Tadayuki Tsutsui ,  Bo Hu ,  Kei Ishii ,  Hideo Shikata ,  Jun Sakai

发明人： Tadayuki Tsutsui ,  Bo Hu ,  Kei Ishii ,  Hideo Shikata ,  Jun Sakai

IPC分类号： F16C35/00 ,  B22F3/10 ,  B22F7/00 ,  C22C33/02 ,  F02F7/00

CPC分类号： B22F3/1003

摘要： There is disclosed a method for manufacturing an Fe-based sintered alloy which is superb in machinability. This process comprises the steps of coating a paste-like coating agent including a compound of boron to a surface of a compact of Fe-based or Fe, Cu-based sintered alloy powder including carbon or a pre-sintered compact obtained by heating the compact at a diffusion temperature or less of carbon, and sintering a resultant compact or a pre-sintered compact at a diffusion temperature or more of carbon. An Fe-based sintered alloy manufactured through this process and a bearing cap made of such an Fe-based sintered alloy are also disclosed. In the invention, a film including a compound of boron and pyrolytic resin can be used instead of the paste-like coating agent.

摘要翻译： 公开了一种制造铁素体烧结合金的方法，该方法在机械加工性方面是极好的。 该方法包括以下步骤：将包含硼化合物的糊状涂层剂涂覆在包含碳的Fe基或Fe，Cu基烧结合金粉末或通过加热该压块获得的预烧结体 在扩散温度以下的碳上，在碳的扩散温度以上烧结得到的压块或预烧结体。 还公开了通过该方法制造的Fe基烧结合金和由这种Fe基烧结合金制成的轴承盖。 在本发明中，可以使用含有硼化合物和热解性树脂的膜代替膏状涂布剂。

公开(公告)号：US5059266A

公开(公告)日：1991-10-22

申请号：US527286

申请日：1990-05-23

申请人： Mitsuo Yamane ,  Takashi Kawaguchi ,  Shigeru Kagayama ,  Shunichi Higashiyama ,  Keiko Suzuki ,  Jun Sakai ,  Mikio Imaeda ,  Kouji Inaishi

发明人： Mitsuo Yamane ,  Takashi Kawaguchi ,  Shigeru Kagayama ,  Shunichi Higashiyama ,  Keiko Suzuki ,  Jun Sakai ,  Mikio Imaeda ,  Kouji Inaishi

IPC分类号： B29C41/08 ,  B29C67/00

CPC分类号： B29C67/0059 ,  B29C41/08 ,  B29C67/0066 ,  G05B2219/49031

摘要： An apparatus and a method for forming a three-dimensional article with photosetting or thermosetting material on the basis of a three-dimensional information on the article by means of an ink jet method. The material is jetted from at least one ink jet head to a stage and laminated thereon. The laminated material is exposed to light by a light source to be cured. In this process, a jetting direction of the material from the ink jet head to the stage and/or a jetting amount of the material jetted from the ink jet head is changed in accordance with the information by a control unit, thereby forming a solid article having a desired three-dimensional shape.

摘要翻译： 基于通过喷墨法对制品的三维信息，用光固化或热固性材料形成三维制品的装置和方法。 将材料从至少一个喷墨头喷射到一个阶段并层压在其上。 层压材料通过待固化的光源曝光。 在该过程中，根据控制单元的信息改变从喷墨头到舞台的材料的喷射方向和/或从喷墨头喷射的材料的喷射量，从而形成固体物品 具有所需的三维形状。

公开(公告)号：US4985727A

公开(公告)日：1991-01-15

申请号：US404775

申请日：1989-09-09

申请人： Jun Sakai ,  Mitsuru Ohta

发明人： Jun Sakai ,  Mitsuru Ohta

IPC分类号： G03D13/00 ,  G03B27/32 ,  G03F7/00

CPC分类号： G03F7/0022 ,  G03B27/32 ,  G03B2227/325

摘要： An image recording apparatus having a first exposure unit for forming a latent image corresponding to an original image on a photosensitive pressure sensitive recording medium, and a second exposure unit for electrostatically forming a developer particle image. The developer particle image is transferred onto the photosensitive pressure sensitive recording medium, and the thus transferred developer particles are reacted with chromogenic material of the photosensitive recording medium at a pressure developing unit so that a visible image is provided on another sheet medium. A method for recording the image includes the steps of effecting a first exposure for forming the latent image, effecting a second exposure for forming the developer particle image, electrostatically transferring the developer particle image onto the recording medium, and pressure developing the image to provide a visible image on a separate plane paper.

摘要翻译： 一种图像记录装置，具有用于在光敏压敏记录介质上形成对应于原始图像的潜像的第一曝光单元和用于静电显影显影剂颗粒图像的第二曝光单元。 将显影剂颗粒图像转印到感光压敏记录介质上，并将这样转印的显影剂颗粒与感光记录介质的显色材料在压力显影单元处反应，使得可见图像被提供在另一个片材介质上。 用于记录图像的方法包括以下步骤：进行用于形成潜像的第一曝光，进行用于形成显影剂颗粒图像的第二曝光，将显影剂颗粒图像静电转印到记录介质上，以及对显影图像进行加压显影， 在单独的平面纸上的可见图像。

公开(公告)号：US4940688A

公开(公告)日：1990-07-10

申请号：US289675

申请日：1988-12-27

申请人： Jun Sakai

发明人： Jun Sakai

IPC分类号： B41M5/333 ,  B41M5/155 ,  G03F7/00

CPC分类号： G03F7/002

摘要： A developer sheet having a high light resistivity comprises a layer having an electrophilic developer coated thereon, and a layer having transparent or semitransparent particles containing an ultraviolet-ray absorbent and a process for producing the developer sheet.

摘要翻译： 具有高光阻率的显影片包括其上涂覆有亲电显影剂的层和具有含有紫外线吸收剂的透明或半透明颗粒的层和用于制备显影剂片的方法。