公开(公告)号：US09691746B2

公开(公告)日：2017-06-27

申请号：US14330805

申请日：2014-07-14

Applicant: Micron Technology, Inc.

Inventor： Sameer S. Vadhavkar ,  Xiao Li ,  Steven K. Groothuis ,  Jian Li ,  Jaspreet S. Gandhi ,  James M. Derderian ,  David R. Hembree

IPC: H01L25/00 ,  H01L21/56 ,  H01L23/00 ,  H01L23/04 ,  H01L21/50 ,  H01L25/065 ,  H01L23/367 ,  H01L23/44 ,  H01L25/18

CPC classification number: H01L25/50 ,  H01L21/50 ,  H01L21/563 ,  H01L23/04 ,  H01L23/3675 ,  H01L23/44 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/1134 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/17519 ,  H01L2224/2919 ,  H01L2224/29191 ,  H01L2224/2929 ,  H01L2224/2939 ,  H01L2224/29393 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2224/83102 ,  H01L2224/83104 ,  H01L2224/83424 ,  H01L2224/83447 ,  H01L2224/8388 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/156 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2924/1815 ,  H01L2924/0715 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/014 ,  H01L2924/01047 ,  H01L2924/00012 ,  H01L2924/0665 ,  H01L2924/00

Abstract: Method for packaging a semiconductor die assemblies. In one embodiment, a method is directed to packaging a semiconductor die assembly having a first die and a plurality of second dies arranged in a stack over the first die, wherein the first die has a peripheral region extending laterally outward from the stack of second dies. The method can comprise coupling a thermal transfer structure to the peripheral region of the first die and flowing an underfill material between the second dies. The underfill material is flowed after coupling the thermal transfer structure to the peripheral region of the first die such that the thermal transfer structure limits lateral flow of the underfill material.

公开(公告)号：US09337119B2

公开(公告)日：2016-05-10

申请号：US14330900

申请日：2014-07-14

Applicant: Micron Technology, Inc.

Inventor： Sameer S. Vadhavkar ,  Xiao Li ,  Jaspreet S. Gandhi

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/34 ,  H01L23/31 ,  H01L25/065

CPC classification number: H01L23/34 ,  H01L23/10 ,  H01L23/3107 ,  H01L23/3677 ,  H01L23/4275 ,  H01L23/473 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/17519 ,  H01L2224/26145 ,  H01L2224/26175 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48145 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/92125 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/16195 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2924/1627 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/00012

Abstract: Semiconductor die assemblies having high efficiency thermal paths. In one embodiment, a semiconductor die assembly comprises a package support substrate, a first semiconductor die electrically mounted to the package support substrate, and a plurality of second semiconductor dies. The first die has a stacking site and a peripheral region extending laterally from the stacking site, and the bottom second semiconductor die is attached to the stacking site of the first die. The assembly further includes (a) a thermal transfer structure attached to the peripheral region of the first die that has a cavity in which the second dies are positioned and an inlet, and (b) an underfill material in the cavity. The underfill material has a fillet between the second semiconductor dies caused by injecting the underfill material into the cavity through the inlet port of the casing.

Abstract translation: 具有高效率热路径的半导体管芯组件。 在一个实施例中，半导体管芯组件包括封装支撑衬底，电气安装到封装支撑衬底的第一半导体管芯和多个第二半导体管芯。 第一模具具有堆叠位置和从堆叠位置​​横向延伸的周边区域，并且底部第二半导体管芯附接到第一管芯的堆叠位置。 组件还包括（a）附接到第一模具的周边区域的热转印结构，其具有第二模具所在的空腔和入口，以及（b）空腔中的底部填充材料。 底部填充材料在第二半导体管芯之间具有由底部填充材料通过壳体的入口注入空腔而引起的圆角。

公开(公告)号：US20150348956A1

公开(公告)日：2015-12-03

申请号：US14825009

申请日：2015-08-12

Applicant: Micron Technology, Inc.

Inventor： Steven K. Groothuis ,  Jian Li ,  Haojun Zhang ,  Paul A. Silvestri ,  Xiao Li ,  Shijan Luo ,  Luke G. England ,  Brent Keeth ,  Jaspreet S. Gandhi

IPC: H01L25/00 ,  H01L23/367 ,  H01L25/065

CPC classification number: H01L23/36 ,  H01L23/3675 ,  H01L23/3677 ,  H01L23/3736 ,  H01L23/42 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06589 ,  H01L2924/15311

Abstract: Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a plurality of first semiconductor dies arranged in a stack and a second semiconductor die carrying the first semiconductor dies. The second semiconductor die can include a peripheral portion that extends laterally outward beyond at least one side of the first semiconductor dies. The semiconductor die assembly can further include a thermal transfer feature at the peripheral portion of the second semiconductor die. The first semiconductor dies can define a first thermal path, and the thermal transfer feature can define a second thermal path separate from the first semiconductor dies.

Abstract translation: 本文公开了具有多个热路径和相关系统和方法的堆叠的半导体管芯组件。 在一个实施例中，半导体管芯组件可以包括布置在堆叠中的多个第一半导体管芯和承载第一半导体管芯的第二半导体管芯。 第二半导体管芯可以包括横向向外延伸超过第一半导体管芯的至少一侧的周边部分。 半导体管芯组件还可以包括在第二半导体管芯的周边部分处的热传递特征。 第一半导体管芯可以限定第一热路径，并且热转移特征可以限定与第一半导体管芯分离的第二热路径。

公开(公告)号：US09157014B2

公开(公告)日：2015-10-13

申请号：US13689144

申请日：2012-11-29

Applicant: Micron Technology, Inc.

Inventor： Shijian Luo ,  Xiao Li

IPC: C09J11/04 ,  H01L21/683 ,  C08K3/00 ,  C08K3/04 ,  C08K3/14 ,  C08K3/22 ,  C08K3/36 ,  C08K7/18

CPC classification number: C09J11/04 ,  C08K3/013 ,  C08K3/04 ,  C08K3/14 ,  C08K3/22 ,  C08K3/36 ,  C08K7/18 ,  C09J2203/326 ,  H01L21/6835 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381

Abstract: Temporary adhesives include a thermoplastic polymer comprising from about 30% by weight to about 80% by weight of the temporary adhesive, a solvent comprising from about 20% by weight to about 70% by weight of the temporary adhesive, and a filler material comprising from about 0.2% to about 5% by weight of the temporary adhesive. Methods of processing a semiconductor device wafer include bonding the semiconductor device wafer to a surface of a carrier substrate using a temporary adhesive including a filler material comprising from about 0.2% to about 5% by weight of the temporary adhesive, thinning the semiconductor device wafer, and, while the temporary adhesive remains on the surface of the carrier substrate proximate a peripheral edge thereof, subjecting the thinned semiconductor device wafer to one or more back side processing operations. Methods of forming a thinned semiconductor wafer include using such a temporary adhesive.

Abstract translation: 临时粘合剂包括热塑性聚合物，其包含约30重量％至约80重量％的临时粘合剂，包含约20重量％至约70重量％的临时粘合剂的溶剂，以及填料， 约0.2％至约5％的临时粘合剂。 处理半导体器件晶片的方法包括使用包括约0.2重量％至约5重量％的临时粘合剂的填充材料的临时粘合剂将半导体器件晶片接合到载体衬底的表面，使半导体器件晶片变薄， 并且当临时粘合剂在其周边附近残留在载体基板的表面上时，对减薄的半导体器件晶片进行一个或多个背面处理操作。 形成薄化半导体晶片的方法包括使用这种临时粘合剂。

公开(公告)号：US20140147989A1

公开(公告)日：2014-05-29

申请号：US13689144

申请日：2012-11-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Shijian Luo ,  Xiao Li

IPC: C09J11/04 ,  H01L21/18

CPC classification number: C09J11/04 ,  C08K3/013 ,  C08K3/04 ,  C08K3/14 ,  C08K3/22 ,  C08K3/36 ,  C08K7/18 ,  C09J2203/326 ,  H01L21/6835 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381

Abstract: Temporary adhesives include a thermoplastic polymer comprising from about 30% by weight to about 80% by weight of the temporary adhesive, a solvent comprising from about 20% by weight to about 70% by weight of the temporary adhesive, and a filler material comprising from about 0.2% to about 5% by weight of the temporary adhesive. Methods of processing a semiconductor device wafer include bonding the semiconductor device wafer to a surface of a carrier substrate using a temporary adhesive including a filler material comprising from about 0.2% to about 5% by weight of the temporary adhesive, thinning the semiconductor device wafer, and, while the temporary adhesive remains on the surface of the carrier substrate proximate a peripheral edge thereof, subjecting the thinned semiconductor device wafer to one or more back side processing operations. Methods of forming a thinned semiconductor wafer include using such a temporary adhesive.

Abstract translation: 临时粘合剂包括热塑性聚合物，其包含约30重量％至约80重量％的临时粘合剂，包含约20重量％至约70重量％的临时粘合剂的溶剂，以及填料， 约0.2％至约5％的临时粘合剂。 处理半导体器件晶片的方法包括使用包括约0.2重量％至约5重量％的临时粘合剂的填充材料的临时粘合剂将半导体器件晶片接合到载体衬底的表面，使半导体器件晶片变薄， 并且当临时粘合剂在其周边附近残留在载体基板的表面上时，对减薄的半导体器件晶片进行一个或多个背面处理操作。 形成薄化半导体晶片的方法包括使用这种临时粘合剂。

公开(公告)号：US20250156923A1

公开(公告)日：2025-05-15

申请号：US19026776

申请日：2025-01-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Carla L. Christensen ,  Bethany M. Grentz ,  Xiao Li ,  Sumana Adusumilli ,  Libo Wang

IPC: G06Q30/0601 ,  G06T19/00

Abstract: A size comparison system may generate a size comparison by determining a size of an item based on extracted size data corresponding to the item. A comparison item is selected and the size comparison is generated between the item and the comparison item based on the size of the item. A visual rendering of the item and the comparison item is generated based on the size comparison and is displayed to a user.

公开(公告)号：US12295140B2

公开(公告)日：2025-05-06

申请号：US17533580

申请日：2021-11-23

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  Allen McTeer ,  Rita J. Klein ,  John D. Hopkins ,  Nancy M. Lomeli ,  Xiao Li ,  Alyssa N. Scarbrough ,  Jiewei Chen ,  Naiming Liu ,  Shuangqiang Luo ,  Silvia Borsari ,  John Mark Meldrim ,  Shen Hu

IPC: H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers in the memory blocks. A through-array-via (TAV) region comprises TAV constructions that extend through the insulative tiers and the conductive tiers. The TAV constructions individually comprise a radially-outer insulative lining and a conductive core radially-inward of the insulative lining. The insulative lining comprises a radially-inner insulative material and a radially-outer insulative material that are of different compositions relative one another. The radially-outer insulative material is in radially-outer recesses that are in the first tiers as compared to the second tiers. The radially-inner insulative material extends elevationally along the insulative tiers and the conductive tiers. Other embodiments, including method, are disclosed.

公开(公告)号：US12094581B2

公开(公告)日：2024-09-17

申请号：US16993175

申请日：2020-08-13

Applicant: Micron Technology, Inc.

Inventor： Libo Wang ,  Xiao Li ,  Bethany M. Grentz ,  Sumana Adusumilli ,  Carla L Christensen

IPC: G16H10/60 ,  G01W1/10 ,  G16H20/70

CPC classification number: G16H10/60 ,  G01W1/10 ,  G16H20/70 ,  G01W2203/00

Abstract: Systems for weather sensing and forecasting, and associated devices and methods, are disclosed herein. In some embodiments, a system for predicting a subject's perception of weather conditions is provided. The system can generate an individual profile for the subject, the individual profile including health information of the subject. The system can receive weather data including a first weather condition for a target location. The system can compare the individual profile to a plurality of different user profiles to identify one or more similar user profiles. Each similar user profile can (1) be associated with a user having similar health information as the subject, and (2) include weather perception data indicating how the user perceived a set of second weather conditions. Based on the weather data and the similar user profile(s), the system can generate a prediction of the how the subject will perceive the first weather condition.

公开(公告)号：US20230395507A1

公开(公告)日：2023-12-07

申请号：US17822726

申请日：2022-08-26

Applicant: Micron Technology, Inc.

Inventor： Xiao Li ,  Jordan D. Greenlee

IPC: H01L23/532 ,  H01L23/528 ,  H01L21/02

CPC classification number: H01L23/5329 ,  H01L23/528 ,  H01L21/0226

Abstract: A microelectronic device comprises a stack structure, a contact structure, a liner material, and a boron-containing material. The stack structure comprises alternating conductive structures and dielectric structures. The contact structure extends through the stack structure. The liner material is between the stack structure and the contact structure. The boron-containing material is between the liner material and the stack structure. Related electronic systems and methods are also described.

公开(公告)号：US11688664B2

公开(公告)日：2023-06-27

申请号：US17140610

申请日：2021-01-04

Applicant: Micron Technology, Inc.

Inventor： Bradley R. Bitz ,  Xiao Li ,  Jaspreet S. Gandhi

IPC: H01L23/427 ,  H01L23/42 ,  H01L23/433 ,  H01L23/46 ,  H01L23/473 ,  H01L25/065

CPC classification number: H01L23/427 ,  H01L23/42 ,  H01L23/4334 ,  H01L23/46 ,  H01L23/473 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/06582 ,  H01L2225/06589

Abstract: Semiconductor device assemblies having stacked semiconductor dies and thermal transfer devices that include vapor chambers are disclosed herein. In one embodiment, a semiconductor device assembly includes a first semiconductor die having a base region, at least one second semiconductor die at the base region, and a thermal transfer device attached to the first and second dies. The thermal transfer device includes an encapsulant at least partially surrounding the second die and a via formed in the encapsulant. The encapsulant at least partially defines a cooling channel that is adjacent to a peripheral region of the first die. The via includes a working fluid and/or a solid thermal conductor that at least partially fills the channel.