公开(公告)号：US10170175B2

公开(公告)日：2019-01-01

申请号：US14705698

申请日：2015-05-06

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kiyoshi Kato ,  Tatsuya Onuki

IPC: G11C11/4096 ,  G11C11/4091 ,  G11C11/4097

Abstract: A memory device with low power consumption is provided. The memory device includes a sense amplifier, bit lines, memory cells, and first transistors. The bit lines are provided over a layer comprising the sense amplifier. The memory cells are provided over a layer comprising the bit lines. The memory cell includes a second transistor and a capacitor. The sense amplifier and the bit lines are electrically connected to each other through the first transistors. The sense amplifier may include at least one layer of a conductor.

公开(公告)号：US10090022B2

公开(公告)日：2018-10-02

申请号：US15626595

申请日：2017-06-19

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yutaka Shionoiri ,  Tomoaki Atsumi ,  Kiyoshi Kato ,  Takanori Matsuzaki

IPC: G11C7/02 ,  G11C5/06 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/24

Abstract: To provide a semiconductor device with a high output voltage. A gate of a first transistor is electrically connected to a first terminal through a first capacitor. A gate of a second transistor is electrically connected to a second terminal through a second capacitor. One of a source and a drain of a third transistor is electrically connected to the gate of the first transistor through a third capacitor. One of a source and a drain of a fourth transistor is electrically connected to the gate of the second transistor through a fourth capacitor. The other of the source and the drain of the third transistor and the other of the source and the drain of the fourth transistor are electrically connected to a high potential power source. A third terminal is electrically connected to one of a source and a drain of the second transistor.

公开(公告)号：US10083996B2

公开(公告)日：2018-09-25

申请号：US14730436

申请日：2015-06-04

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei Yamazaki ,  Jun Koyama ,  Kiyoshi Kato

IPC: H01L29/24 ,  H01L27/12 ,  H01L21/84 ,  H01L27/108 ,  H01L27/11 ,  H01L27/11517 ,  H01L27/11521 ,  H01L27/1156 ,  H01L27/118 ,  H01L29/786 ,  G11C16/04 ,  G11C16/26

CPC classification number: H01L27/1255 ,  G11C16/0433 ,  G11C16/26 ,  H01L21/84 ,  H01L27/108 ,  H01L27/10805 ,  H01L27/10873 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/11517 ,  H01L27/11521 ,  H01L27/1156 ,  H01L27/11803 ,  H01L27/1225 ,  H01L29/24 ,  H01L29/7869

Abstract: An object of the present invention is to provide a semiconductor device having a novel structure in which in a data storing time, stored data can be stored even when power is not supplied, and there is no limitation on the number of writing. A semiconductor device includes a first transistor including a first source electrode and a first drain electrode; a first channel formation region for which an oxide semiconductor material is used and to which the first source electrode and the first drain electrode are electrically connected; a first gate insulating layer over the first channel formation region; and a first gate electrode over the first gate insulating layer. One of the first source electrode and the first drain electrode of the first transistor and one electrode of a capacitor are electrically connected to each other.

公开(公告)号：US09998104B2

公开(公告)日：2018-06-12

申请号：US14945499

申请日：2015-11-19

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Takanori Matsuzaki ,  Kiyoshi Kato

IPC: H03K5/153 ,  H03K5/24

CPC classification number: H03K5/24 ,  G11C11/5642

Abstract: In a configuration including a first circuit for retaining a plurality of analog voltages and a second circuit capable of reading one of the analog voltages as a digital signal, correct data can be read even when characteristics of transistors in the first and second circuits vary with the temperature change. A reference voltage is applied to a gate of a transistor in the second circuit whose threshold voltage varies with the temperature change, and a corrected reference voltage is generated by adding a threshold voltage variation of the transistor in the second circuit to the reference voltage. An analog voltage is read out as a digital signal with the use of the corrected reference voltage, resulting in readout of correct data obtained by canceling out variations in characteristics due to the temperature change of the transistor in the first circuit.

公开(公告)号：US09953695B2

公开(公告)日：2018-04-24

申请号：US15390920

申请日：2016-12-27

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Takayuki Ikeda ,  Yutaka Shionoiri ,  Kiyoshi Kato ,  Tomoaki Atsumi

IPC: G11C5/14 ,  G11C11/4074 ,  G11C11/4096 ,  G11C11/4094 ,  H01L29/786 ,  H01L27/115 ,  H01L27/108

CPC classification number: G11C11/4074 ,  G11C5/146 ,  G11C5/147 ,  G11C11/403 ,  G11C11/4094 ,  G11C11/4096 ,  H01L27/10805 ,  H01L27/115 ,  H01L28/00 ,  H01L29/78648 ,  H01L29/7869

Abstract: A semiconductor device capable of stably holding data for a long time is provided. A transistor including a back gate is used as a writing transistor of a memory element. In the case where the transistor is an n-channel transistor, a negative potential is supplied to a back gate in holding memory. The supply of the negative potential is stopped while the negative potential is held in the back gate. In the case where an increase in the potential of the back gate is detected, the negative potential is supplied to the back gate.

公开(公告)号：US09922685B2

公开(公告)日：2018-03-20

申请号：US14068131

申请日：2013-10-31

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Jun Koyama ,  Kiyoshi Kato

IPC: G11C11/40 ,  G11C7/06 ,  H01L27/06 ,  H01L27/105 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/12 ,  H01L29/15 ,  H01L29/205 ,  H01L21/02

CPC classification number: G11C7/062 ,  G11C7/067 ,  G11C11/40 ,  G11C2207/005 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/1203 ,  H01L27/1225 ,  H01L29/155 ,  H01L29/205

Abstract: A semiconductor device includes: a source line; a bit line; a word line; a memory cell connected to the bit line and the word line; a driver circuit which drives a plurality of second signal lines and a plurality of word lines so as to select the memory cell specified by an address signal; a potential generating circuit which generates a writing potential and a plurality of reading potentials to supply to a writing circuit and a reading circuit; and a control circuit which selects one of a plurality of voltages for correction on a basis of results of the reading circuit comparing a potential of the bit line with the plurality of reading potentials.

公开(公告)号：US09859905B2

公开(公告)日：2018-01-02

申请号：US14862284

申请日：2015-09-23

Applicant: Semiconductor Energy Laboratory Co., LTD.

Inventor： Yutaka Shionoiri ,  Kiyoshi Kato ,  Tomoaki Atsumi

IPC: H03M1/00 ,  H03M1/12 ,  G11C27/02 ,  H03M1/46

CPC classification number: H03M1/002 ,  G11C27/02 ,  H03M1/1245 ,  H03M1/466

Abstract: An object is to reduce power consumption of an analog-digital converter circuit. An analog potential obtained in a sensor or the like is held in a sample-and-hold circuit including a transistor with an extremely low off-state current. In the sample-and-hold circuit, the analog potential is held in a node which is able to hold a charge by turning off the transistor. Then, power supply to a buffer circuit or the like included in the sample-and-hold circuit is stopped to reduce power consumption. In a structure where a potential is held in each node, power consumption can be further reduced when a transistor with an extremely low off-state current is connected to a node holding a potential of a comparator, a successive approximation register, a digital-analog converter circuit, or the like, and power supply to these circuits is stopped.

公开(公告)号：US09705005B2

公开(公告)日：2017-07-11

申请号：US14828669

申请日：2015-08-18

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Jun Koyama ,  Kiyoshi Kato

IPC: H01L29/66 ,  H01L29/786 ,  G11C16/04 ,  G11C16/28 ,  H01L21/02 ,  H01L27/06 ,  H01L27/105 ,  H01L27/108 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/12 ,  G11C11/24 ,  H01L29/26 ,  H01L29/22 ,  G11C5/06 ,  G11C5/14 ,  G11C7/12 ,  H01L23/528 ,  H01L29/24 ,  H01L29/78 ,  H01L27/115 ,  G11C7/18 ,  G11C11/4097

CPC classification number: G11C7/10 ,  G11C5/06 ,  G11C5/147 ,  G11C7/12 ,  G11C7/18 ,  G11C7/22 ,  G11C8/08 ,  G11C11/24 ,  G11C11/4097 ,  G11C16/0433 ,  G11C16/28 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L23/528 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/108 ,  H01L27/115 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/1207 ,  H01L27/1225 ,  H01L29/22 ,  H01L29/24 ,  H01L29/26 ,  H01L29/78 ,  H01L29/78603 ,  H01L29/7869 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An object of the present invention is to provide a semiconductor device combining transistors integrating on a same substrate transistors including an oxide semiconductor in their channel formation region and transistors including non-oxide semiconductor in their channel formation region. An application of the present invention is to realize substantially non-volatile semiconductor memories which do not require specific erasing operation and do not suffer from damages due to repeated writing operation. Furthermore, the semiconductor device is well adapted to store multivalued data. Manufacturing methods, application circuits and driving/reading methods are explained in details in the description.

公开(公告)号：US09704562B2

公开(公告)日：2017-07-11

申请号：US14872535

申请日：2015-10-01

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tatsuya Onuki ,  Kiyoshi Kato ,  Wataru Uesugi ,  Takahiko Ishizu

IPC: G11C7/00 ,  G11C11/4091 ,  G11C7/02 ,  G11C11/4094 ,  G11C11/4097 ,  H01L27/108 ,  G11C5/02

CPC classification number: G11C11/4091 ,  G11C5/025 ,  G11C7/02 ,  G11C11/4094 ,  G11C11/4097 ,  G11C2213/71 ,  H01L27/10808

Abstract: A semiconductor device with low power consumption or a semiconductor device with a reduced area is provided. The semiconductor device includes a cell array including a first memory cell and a second memory cell; and a sense amplifier circuit including a first sense amplifier and a second sense amplifier. The cell array is over the sense amplifier circuit. The first sense amplifier is electrically connected to the first memory cell through a first wiring BL. The second sense amplifier is electrically connected to the second memory cell through a second wiring BL. The first sense amplifier and the second sense amplifier are electrically connected to a wiring GBL. The sense amplifier circuit is configured to select one of a potential of the first wiring BL and a potential of the second wiring BL and output the selected potential to the wiring GBL.

公开(公告)号：US09692421B2

公开(公告)日：2017-06-27

申请号：US13667292

申请日：2012-11-02

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kiyoshi Kato ,  Jun Koyama

IPC: H01L25/00 ,  H03K19/00 ,  H03K19/173 ,  G11C14/00 ,  H01L21/8258 ,  H01L21/84 ,  H01L27/06 ,  H01L27/088 ,  H01L27/12 ,  H01L29/786 ,  H03K3/356 ,  G11C16/02 ,  H01L27/1156

CPC classification number: H03K19/1733 ,  G11C14/0063 ,  G11C16/02 ,  H01L21/8258 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/1156 ,  H01L27/1203 ,  H01L27/1225 ,  H01L29/7869 ,  H03K3/356008 ,  H03K3/35606

Abstract: A novel non-volatile latch circuit and a semiconductor device using the non-volatile latch circuit are provided. The latch circuit has a loop structure in which an output of a first element is electrically connected to an input of a second element and an output of the second element is electrically connected to an input of the first element through a second transistor. A transistor using an oxide semiconductor as a semiconductor material of a channel formation region is used as a switching element, and a capacitor is provided to be electrically connected to a source electrode or a drain electrode of the transistor, whereby data of the latch circuit can be retained, and a non-volatile latch circuit can thus be formed.