公开(公告)号：US07067856B2

公开(公告)日：2006-06-27

申请号：US10768108

申请日：2004-02-02

Applicant: Jamal Ramdani ,  Ravindranath Droopad ,  Lyndee L. Hilt ,  Kurt Williamson Eisenbeiser

Inventor： Jamal Ramdani ,  Ravindranath Droopad ,  Lyndee L. Hilt ,  Kurt Williamson Eisenbeiser

IPC: H01L31/072

CPC classification number: H01S5/0261 ,  C30B25/18 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02439 ,  H01L21/02472 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02507 ,  H01L21/02513 ,  H01L21/02521 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02557 ,  H01L21/0256 ,  H01L21/31691 ,  H01L21/8252 ,  H01L21/8258 ,  H01L27/0605 ,  H01L27/15 ,  H01L33/16 ,  H01L33/30 ,  H01L2924/0002 ,  H01S5/021 ,  H01L2924/00

Abstract: High quality epitaxial layers of compound semiconductor materials can be grown overlying large silicon wafers by first growing an accommodating buffer layer on a silicon wafer. The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline compound semiconductor layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer.

公开(公告)号：US07009270B2

公开(公告)日：2006-03-07

申请号：US10755007

申请日：2004-01-08

Applicant: Fabrice Letertre ,  Bruno Ghyselen ,  Oliver Rayssac

Inventor： Fabrice Letertre ,  Bruno Ghyselen ,  Oliver Rayssac

IPC: H01L29/00

CPC classification number: H01L21/187 ,  B81C1/00365 ,  B81C2201/0191 ,  C30B25/183 ,  H01L21/0237 ,  H01L21/0243 ,  H01L21/02439 ,  H01L21/0245 ,  H01L21/02513 ,  H01L21/02658 ,  H01L21/02664 ,  H01L21/76254

Abstract: A stress absorbing microstructure assembly including a support substrate having an accommodation layer that has plurality of motifs engraved or etched in a surface, a buffer layer and a nucleation layer. The stress absorbing microstructure assembly may also include an insulating layer between the buffer layer and the nucleation layer. This assembly can receive thick epitaxial layers thereon with concern of causing cracking of such layers.

Abstract translation: 一种应力吸收微结构组件，包括具有在表面上雕刻或蚀刻的多个图案的容纳层的支撑衬底，缓冲层和成核层。 应力吸收微结构组件还可以包括缓冲层和成核层之间的绝缘层。 该组件可以在其上接收厚的外延层，同时引起这种层的破裂。

公开(公告)号：US20060022247A1

公开(公告)日：2006-02-02

申请号：US11215614

申请日：2005-08-30

Applicant: Zhiping Yin ,  Weimin Li

Inventor： Zhiping Yin ,  Weimin Li

IPC: H01L29/94 ,  H01L27/108

CPC classification number: H01L21/02115 ,  H01L21/0214 ,  H01L21/022 ,  H01L21/02274 ,  H01L21/0237 ,  H01L21/02439 ,  H01L21/02505 ,  H01L21/02527 ,  H01L21/0262 ,  H01L21/0332 ,  H01L21/3081 ,  H01L21/3146 ,  H01L27/10852

Abstract: A transparent amorphous carbon layer is formed. The transparent amorphous carbon layer has a low absorption coefficient such that the amorphous carbon is transparent in visible light. The transparent amorphous carbon layer may be used in semiconductor devices for different purposes. The transparent amorphous carbon layer may be included in a final structure in semiconductor devices. The transparent amorphous carbon layer may also be used as a mask in an etching process during fabrication of semiconductor devices.

公开(公告)号：US06991998B2

公开(公告)日：2006-01-31

申请号：US10883883

申请日：2004-07-02

Applicant: Stephen W. Bedell ,  Anthony G. Domenicucci ,  Keith E. Fogel ,  Effendi Leobandung ,  Devendra K. Sadana

Inventor： Stephen W. Bedell ,  Anthony G. Domenicucci ,  Keith E. Fogel ,  Effendi Leobandung ,  Devendra K. Sadana

IPC: H01L21/20

CPC classification number: H01L29/78696 ,  H01L21/0237 ,  H01L21/02439 ,  H01L21/02488 ,  H01L21/02502 ,  H01L21/02521 ,  H01L21/02667 ,  H01L21/02694 ,  H01L21/76251 ,  H01L29/7842

Abstract: A method of forming a semiconductor structure comprising a first strained semiconductor layer over an insulating layer is provided in which the first strained semiconductor layer is relatively thin (less than about 500 Å) and has a low defect density (stacking faults and threading defects). The method of the present invention begins with forming a stress-providing layer, such a SiGe alloy layer over a structure comprising a first semiconductor layer that is located atop an insulating layer. The stress-providing layer and the first semiconductor layer are then patterned into at least one island and thereafter the structure containing the at least one island is heated to a temperature that causes strain transfer from the stress-providing layer to the first semiconductor layer. After strain transfer, the stress-providing layer is removed from the structure to form a first strained semiconductor island layer directly atop said insulating layer.

Abstract translation: 提供了一种在绝缘层上形成包括第一应变半导体层的半导体结构的方法，其中第一应变半导体层相对较薄（小于约）并且具有低缺陷密度（堆垛层错和穿线缺陷）。 本发明的方法开始于在包括位于绝缘层顶部的第一半导体层的结构上形成应力提供层，例如SiGe合金层。 然后将应力提供层和第一半导体层图案化成至少一个岛，然后将含有至少一个岛的结构加热到使得应力转移从应力提供层到第一半导体层的温度。 在应变转移之后，将应力提供层从结构上去除，以形成直接位于所述绝缘层顶部的第一应变半导体岛层。

公开(公告)号：US20060001089A1

公开(公告)日：2006-01-05

申请号：US10883883

申请日：2004-07-02

Applicant: Stephen Bedell ,  Anthony Domenicucci ,  Keith Fogel ,  Effendi Leobandung ,  Devendra Sadana

Inventor： Stephen Bedell ,  Anthony Domenicucci ,  Keith Fogel ,  Effendi Leobandung ,  Devendra Sadana

IPC: H01L31/0392 ,  H01L21/84

CPC classification number: H01L29/78696 ,  H01L21/0237 ,  H01L21/02439 ,  H01L21/02488 ,  H01L21/02502 ,  H01L21/02521 ,  H01L21/02667 ,  H01L21/02694 ,  H01L21/76251 ,  H01L29/7842

Abstract: A method of forming a semiconductor structure comprising a first strained semiconductor layer over an insulating layer is provided in which the first strained semiconductor layer is relatively thin (less than about 500 Å) and has a low defect density (stacking faults and threading defects). The method of the present invention begins with forming a stress-providing layer, such a SiGe alloy layer over a structure comprising a first semiconductor layer that is located atop an insulating layer. The stress-providing layer and the first semiconductor layer are then patterned into at least one island and thereafter the structure containing the at least one island is heated to a temperature that causes strain transfer from the stress-providing layer to the first semiconductor layer. After strain transfer, the stress-providing layer is removed from the structure to form a first strained semiconductor island layer directly atop said insulating layer.

Abstract translation: 提供了一种在绝缘层上形成包括第一应变半导体层的半导体结构的方法，其中第一应变半导体层相对较薄（小于约）并且具有低缺陷密度（堆垛层错和穿线缺陷）。 本发明的方法开始于在包括位于绝缘层顶部的第一半导体层的结构上形成应力提供层，例如SiGe合金层。 然后将应力提供层和第一半导体层图案化成至少一个岛，然后将含有至少一个岛的结构加热到使得应力转移从应力提供层到第一半导体层的温度。 在应变转移之后，将应力提供层从结构上去除，以形成直接位于所述绝缘层顶部的第一应变半导体岛层。

公开(公告)号：US20050287691A1

公开(公告)日：2005-12-29

申请号：US11024801

申请日：2004-12-30

Applicant: Hsueh-Shih Chen ,  Dai-Luon Lo ,  Chien-Ming Chen ,  Gwo-Yang Chang

Inventor： Hsueh-Shih Chen ,  Dai-Luon Lo ,  Chien-Ming Chen ,  Gwo-Yang Chang

IPC: C23C18/08 ,  H01L21/00 ,  H01L21/22 ,  H01L21/368

CPC classification number: B82Y30/00 ,  B82Y10/00 ,  C23C18/08 ,  H01L21/02409 ,  H01L21/02439 ,  H01L21/0256 ,  H01L21/02581 ,  H01L21/02601 ,  H01L21/02628 ,  Y10S977/774

Abstract: A doping method for forming quantum dots is disclosed, which includes following steps: providing a first precursor solution for a group II element and a second precursor solution for a group VI element; heating and mixing the first precursor solution and the second precursor solution for forming a plurality of II-VI compound cores of the quantum dots dispersing in a melting mixed solution; and injecting a third precursor solution for a group VI element and a forth precursor solution with at least one dopant to the mixed solution in turn at a fixed time interval in order to form quantum dots with multi-shell dopant; wherein the dopant described here is selected from a group consisting of transitional metal and halogen elements. This method of the invention can dope the dopants in the inner quantum dot and enhance the emission intensity efficiently.

Abstract translation: 公开了一种用于形成量子点的掺杂方法，其包括以下步骤：为第Ⅵ族元素提供第一前体溶液和为Ⅵ族元素提供第二前体溶液; 加热和混合第一前体溶液和第二前体溶液，以形成分散在熔融混合溶液中的量子点的多个II-VI化合物核心; 并且以固定的时间间隔依次向所述混合溶液中注入具有至少一种掺杂剂的第Ⅵ族元素和第四前体溶液的第三前体溶液，以形成具有多壳掺杂剂的量子点; 其中这里描述的掺杂剂选自由过渡金属和卤素元素组成的组。 本发明的这种方法可以掺杂在内量子点中并有效地提高发射强度。

公开(公告)号：US20050229837A1

公开(公告)日：2005-10-20

申请号：US10512077

申请日：2003-05-07

Applicant: Olivier Marty ,  Volodymyr Lysenko

Inventor： Olivier Marty ,  Volodymyr Lysenko

IPC: B05D3/00 ,  B32B15/00 ,  B81C1/00 ,  B82B3/00 ,  C30B25/02 ,  H01L21/20 ,  H01L21/205 ,  H01L39/24 ,  H01L41/22 ,  H01L41/332 ,  C30B33/06 ,  C30B1/00 ,  C30B23/00 ,  C30B25/00

CPC classification number: B81C1/0038 ,  B81C1/00714 ,  C30B25/02 ,  H01L21/0237 ,  H01L21/02381 ,  H01L21/02439 ,  H01L21/02463 ,  H01L21/02513 ,  H01L21/02521 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/0259 ,  H01L21/02658 ,  H01L39/2454 ,  H01L41/332 ,  Y10S977/72 ,  Y10S977/811 ,  Y10S977/825 ,  Y10S977/832 ,  Y10T428/24802

Abstract: The invention relates to a process for modifying the properties of a thin layer (1) formed on the surface of a support (2) forming a substrate (3) utilised in the field of microelectronics, nanoelectronics or microtechnology, nanotechnology, characterised in that it consists of: forming at least one thin layer (1) on a nanostructured support with specific upper surface (2), and treating the nanostructured support with specific upper surface (2) to generate internal strains in the support causing its deformation at least in the plane of the thin layer so as to ensure corresponding deformation of the thin layer to modify its properties.

Abstract translation: 本发明涉及一种用于改变在微电子学，纳米电子学或微技术领域中使用的形成衬底（3）的支撑体（2）的表面上形成的薄层（1）的性质的方法，其特征在于它 包括：在具有特定上表面（2）的纳米结构支撑件上形成至少一个薄层（1），以及用特定上表面（2）处理纳米结构支撑件以在支撑件中产生内部应变，使其至少在 平面，以确保薄层的相应变形，以改变其性能。

公开(公告)号：US20050056835A1

公开(公告)日：2005-03-17

申请号：US10789736

申请日：2004-02-27

Applicant: Zhiping Yin ,  David Williams ,  Weimin Li

Inventor： Zhiping Yin ,  David Williams ,  Weimin Li

IPC: H01L21/314 ,  H01L29/04

CPC classification number: H01L21/02115 ,  H01L21/0214 ,  H01L21/022 ,  H01L21/02274 ,  H01L21/0237 ,  H01L21/02439 ,  H01L21/02505 ,  H01L21/02527 ,  H01L21/0262 ,  H01L21/0332 ,  H01L21/3081 ,  H01L21/3146 ,  H01L27/10852

Abstract: A transparent amorphous carbon layer is formed. The transparent amorphous carbon layer has a low absorption coefficient such that the amorphous carbon is transparent in visible light. The transparent amorphous carbon layer may be used in semiconductor devices for different purposes. The transparent amorphous carbon layer may be included in a final structure in semiconductor devices. The transparent amorphous carbon layer may also be used as a mask in an etching process during fabrication of semiconductor devices.

Abstract translation: 形成透明无定形碳层。 透明无定形碳层具有低吸收系数，使得无定形碳在可见光下是透明的。 透明无定形碳层可用于不同目的的半导体器件中。 透明无定形碳层可以包括在半导体器件中的最终结构中。 在制造半导体器件期间，透明非晶碳层也可用作蚀刻工艺中的掩模。

公开(公告)号：US06693298B2

公开(公告)日：2004-02-17

申请号：US09908707

申请日：2001-07-20

Applicant: Kurt W. Eisenbeiser ,  Zhiyi Yu ,  Ravindranath Droopad

Inventor： Kurt W. Eisenbeiser ,  Zhiyi Yu ,  Ravindranath Droopad

IPC: H01L2904

CPC classification number: H01L21/7624 ,  C30B25/18 ,  H01L21/02381 ,  H01L21/02439 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02532

Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. A monocrystalline layer is then formed over the accommodating buffer layer, such that a lattice constant of the monocrystalline layer substantially matches the lattice constant of a subsequently grown monocrystalline film.

Abstract translation: 通过形成用于生长单晶层的柔性衬底，可以将单晶材料的高质量外延层生长在覆盖单晶衬底（例如大硅晶片）上。 容纳缓冲层包括通过硅氧化物的非晶界面层与硅晶片间隔开的单晶氧化物层。 非晶界面层消耗应变并允许高质量单晶氧化物容纳缓冲层的生长。 容纳缓冲层与下面的硅晶片和上覆的单晶材料层晶格匹配。 然后在容纳缓冲层上形成单晶层，使得单晶层的晶格常数与随后生长的单晶膜的晶格常数基本一致。

公开(公告)号：US06653166B2

公开(公告)日：2003-11-25

申请号：US09851730

申请日：2001-05-09

Applicant: Nikolai Ledentsov

Inventor： Nikolai Ledentsov

IPC: H01L2100

CPC classification number: C30B25/18 ,  B82Y10/00 ,  B82Y20/00 ,  H01L21/0237 ,  H01L21/02395 ,  H01L21/02439 ,  H01L21/02463 ,  H01L21/02507 ,  H01L21/02521 ,  H01L21/02546 ,  H01L21/3245 ,  H01L33/0062 ,  H01S5/22 ,  H01S5/3201 ,  H01S2301/173 ,  H01S2304/12 ,  Y10S438/902 ,  Y10S438/962

Abstract: The method produces coherent dislocation-free regions from initially dislocated and/or defect-rich lattice mismatched layer grown on top of the substrate having a different lattice constant, which does not contain any processing steps before of after the lattice-mismatched layer growth. The process preferably uses in situ formation of a cap layer on top of a dislocated layer. The cap layer preferably has a lattice parameter close to that in the underlying substrate, and different from that in the lattice mismatched layer in no strain state. Under these conditions, the cap layer undergoes elastic repulsion from the regions in the vicinity of the dislocations, where the lattice parameter is the most different from that in the substrate. The cap layer is absent in these regions. When the cap layer has a lower thermal evaporation rate than the underlying lattice-mismatched layer, the regions of this lattice-mismatched layer containing dislocations are selectively evaporated at high enough temperatures, and only the coherent defect-free regions of the initially defect-rich lattice-mismatched layer remain on the substrate. In one embodiment of the invention, the defect-free regions are formed on the substrate with a size preferably tuned in the range of 30-1000 nm, depending on the annealing conditions, thickness of the cap layer, and the lattice mismatch. A device created by this method is also disclosed.