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    Methods and structures for a split gate memory cell structure
    71.
    发明授权
    Methods and structures for a split gate memory cell structure 有权
    分离栅极存储单元结构的方法和结构

    公开(公告)号：US09590058B2

    公开(公告)日：2017-03-07

    申请号：US13929924

    申请日：2013-06-28

    Applicant: Cheong Min Hong ,  Sung-Taeg Kang

    Inventor： Cheong Min Hong ,  Sung-Taeg Kang

    IPC: H01L29/788 ,  H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L27/105 ,  H01L27/115

    CPC classification number: H01L29/42328 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/28518 ,  H01L27/105 ,  H01L27/11536 ,  H01L29/42332 ,  H01L29/45 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/7882

    Abstract: A method of forming a split gate memory cell structure using a substrate includes forming a gate stack comprising a select gate and a dielectric portion overlying the select gate. A charge storage layer is formed over the substrate including over the gate stack. A first sidewall spacer of conductive material is formed along a first sidewall of the gate stack extending past a top of the select gate. A second sidewall spacer of dielectric material is formed along the first sidewall on the first sidewall spacer. A portion of the first sidewall spacer is silicided using the second sidewall spacer as a mask whereby silicide does not extend to the charge storage layer.

    Abstract translation: 使用衬底形成分离栅极存储单元结构的方法包括形成包括选择栅极和覆盖在选择栅极上的电介质部分的栅极堆叠。 电荷存储层形成在包括栅叠层上的衬底上。 导电材料的第一侧壁间隔物沿着延伸经过选择栅极的顶部的栅极堆叠的第一侧壁形成。 电介质材料的第二侧壁间隔物沿着第一侧壁间隔件上的第一侧壁形成。 使用第二侧壁间隔物作为掩模使第一侧壁间隔物的一部分硅化，由此硅化物不延伸到电荷存储层。

    CRYSTAL ORIENTATION LAYER LAMINATED STRUCTURE, ELECTRONIC MEMORY AND METHOD FOR MANUFACTURING CRYSTAL ORIENTATION LAYER LAMINATED STRUCTURE
    73.
    发明申请
    CRYSTAL ORIENTATION LAYER LAMINATED STRUCTURE, ELECTRONIC MEMORY AND METHOD FOR MANUFACTURING CRYSTAL ORIENTATION LAYER LAMINATED STRUCTURE 审中-公开
    晶体取向层叠结构，电子记忆及制造晶体取向层叠层结构的方法

    公开(公告)号：US20170062711A1

    公开(公告)日：2017-03-02

    申请号：US15349074

    申请日：2016-11-11

    Applicant: National Institute of Advanced Industrial Science and Technology

    Inventor： Yuta Saito ,  Junji Tominaga ,  Reiko Kondo

    IPC: H01L45/00 ,  C23C14/34

    CPC classification number: H01L45/06 ,  C23C14/34 ,  C30B23/025 ,  C30B29/46 ,  C30B29/68 ,  G11C11/161 ,  H01L27/105 ,  H01L29/82 ,  H01L45/143 ,  H01L45/144 ,  H01L45/1625

    Abstract: A crystal orientation layer laminated structure capable of widely selecting materials for a base substrate and an electrode substrate, an electronic memory using the crystal orientation layer laminated structure and a method for manufacturing the crystal orientation layer laminated structure are provided. The crystal orientation layer laminated structure according to the present invention has such a feature as including a substrate, including an orientation control layer which is laminated on the substrate, which is made of any of germanium, silicon, tungsten, germanium-silicon, germanium-tungsten and silicon-tungsten, and whose thickness is at least 1 nm or more, and including a first crystal orientation layer which is laminated on the orientation control layer, which is made of any of SbTe, Sb2Te3, BiTe, Bi2Te3, BiSe and Bi2Se3 as a main component, and which is oriented in a certain crystal orientation

    Abstract translation: 提供能够广泛选择用于基底基板和电极基板的材料的晶体取向层层叠结构，使用晶体取向层叠结构的电子存储器以及晶体取向层层叠结构的制造方法。 根据本发明的晶体取向层层叠结构具有包括基板的特征，该基板包括层叠在基板上的取向控制层，该取向控制层由锗，硅，钨，锗 - 硅，锗 - 钨和硅 - 钨，并且其厚度为至少1nm以上，并且包括层叠在取向控制层上的由SbTe，Sb2Te3，BiTe，Bi2Te3，BiSe和Bi2Se3中的任一种制成的第一晶体取向层 作为主要成分，其取向为一定的晶体取向

    VOLTAGE REGULATOR CIRCUIT
    74.
    发明申请
    VOLTAGE REGULATOR CIRCUIT 有权
    电压调节器电路

    公开(公告)号：US20170054034A1

    公开(公告)日：2017-02-23

    申请号：US15249570

    申请日：2016-08-29

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Shunpei Yamazaki ,  Hiroyuki Miyake ,  Masashi Tsubuku ,  Kosei Noda

    IPC: H01L29/786 ,  H02M3/158 ,  H01L29/66 ,  H01L27/12 ,  H01L29/24

    CPC classification number: H01L29/78696 ,  H01L21/84 ,  H01L27/105 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/7869 ,  H02M3/073 ,  H02M3/158

    Abstract: A transistor includes a gate, a source, and a drain, the gate is electrically connected to the source or the drain, a first signal is input to one of the source and the drain, and an oxide semiconductor layer whose carrier concentration is 5×1014/cm3 or less is used for a channel formation layer. A capacitor includes a first electrode and a second electrode, the first electrode is electrically connected to the other of the source and the drain of the transistor, and a second signal which is a clock signal is input to the second electrode. A voltage of the first signal is stepped up or down to obtain a third signal which is output as an output signal through the other of the source and the drain of the transistor.

    Abstract translation: 晶体管包括栅极，源极和漏极，栅极电连接到源极或漏极，第一信号被输入到源极和漏极中的一个，以及载流子浓度为5× 1014 / cm3以下用于沟道形成层。 电容器包括第一电极和第二电极，第一电极电连接到晶体管的源极和漏极中的另一个，并且作为时钟信号的第二信号被输入到第二电极。 第一信号的电压被升高或降低以获得通过晶体管的源极和漏极中的另一个输出作为输出信号的第三信号。

    TECHNIQUES FOR FORMING VERTICAL TRANSISTOR ARCHITECTURES
    75.
    发明申请
    TECHNIQUES FOR FORMING VERTICAL TRANSISTOR ARCHITECTURES 审中-公开
    形成垂直晶体管结构的技术

    公开(公告)号：US20170025412A1

    公开(公告)日：2017-01-26

    申请号：US15124808

    申请日：2014-06-23

    Applicant: KIMIN JUN ,  PATRICK MORROW

    Inventor： KIMIN JUN ,  PATRICK MORROW

    IPC: H01L27/088 ,  H01L23/528 ,  H01L21/8238 ,  H01L29/06 ,  H01L27/092 ,  H01L21/8234 ,  H01L29/78

    CPC classification number: H01L27/088 ,  H01L21/823475 ,  H01L21/823487 ,  H01L21/823871 ,  H01L21/823885 ,  H01L23/528 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/105 ,  H01L27/11273 ,  H01L28/00 ,  H01L29/0676 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66666 ,  H01L29/775 ,  H01L29/7827 ,  H01L29/7926

    Abstract: Techniques are disclosed for forming vertical transistor architectures. In accordance with some embodiments, a semiconductor layer is disposed over a lower interconnect layer and patterned into a plurality of vertical semiconductor bodies (e.g., nanowires and/or other three-dimensional semiconductor structures) in a regular, semi-regular, or irregular array, as desired for a given target application or end-use. Thereafter, a gate layer surrounding the active channel portion of each (or some sub-set) of the vertical semiconductor bodies is formed, followed by an upper interconnect layer, in accordance with some embodiments. During processing, a given vertical semiconductor body optionally may be removed and, in accordance with some embodiments, either: (1) blanked to provide a dummy channel; or (2) replaced with an electrically conductive plug to provide a via or other inter-layer routing. Processing can be performed in multiple iterations, for example, to provide multi-level/stacked vertical transistor circuit architectures of any standard and/or custom configuration.

    Abstract translation: 公开了用于形成垂直晶体管架构的技术。 根据一些实施例，半导体层设置在下互连层上并且被图案化成规则的，半规则的或不规则的阵列中的多个垂直半导体体（例如，纳米线和/或其他三维半导体结构） ，如针对给定的目标应用或最终用途所希望的。 此后，根据一些实施例，形成围绕垂直半导体主体的每个（或某些子组）的有源沟道部分的栅极层，随后是上部互连层。 在处理期间，任选地可以去除给定的垂直半导体体，并且根据一些实施例，可以：（1）消隐以提供虚拟通道; 或（2）用导电插头替代以提供通孔或其它层间布线。 可以在多次迭代中执行处理，例如，提供任何标准和/或定制配置的多级/堆叠垂直晶体管电路架构。

    Capacitor and method for making same
    76.
    发明授权
    Capacitor and method for making same 有权
    电容器及其制作方法

    公开(公告)号：US09553095B2

    公开(公告)日：2017-01-24

    申请号：US14103307

    申请日：2013-12-11

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Kuo-Chi Tu ,  Wen-Chuan Chiang ,  Chen-Jong Wang

    IPC: H01L27/108 ,  H01L23/522 ,  H01L27/105 ,  H01L27/11 ,  H01L49/02

    CPC classification number: H01L28/60 ,  H01L23/5223 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/108 ,  H01L27/10894 ,  H01L27/11 ,  H01L27/1116 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A system-on-chip (SOC) device comprises a first capacitor in a first region, a second capacitor in a second region, and may further comprise a third capacitor in a third region, and any additional number of capacitors in additional regions. The capacitors may be of different shapes and sizes. A region may comprise more than one capacitor. Each capacitor in a region has a top electrode, a bottom electrode, and a capacitor insulator. The top electrodes of all the capacitors are formed in a common process, while the bottom electrodes of all the capacitors are formed in a common process. The capacitor insulator may have different number of sub-layers, formed with different materials or different thickness. The capacitors may be formed in an inter-layer dielectric layer or in an inter-metal dielectric layer. The regions may be a mixed signal region, an analog region, a radio frequency region, a dynamic random access memory region, and so forth.

    Abstract translation: 片上系统（SOC）装置包括第一区域中的第一电容器，第二区域中的第二电容器，以及可以在第三区域中包括第三电容器，以及附加区域中的任何附加数量的电容器。 电容器可以具有不同的形状和尺寸。 区域可以包括多于一个的电容器。 区域中的每个电容器具有顶部电极，底部电极和电容器绝缘体。 所有电容器的顶部电极以公共工艺形成，而所有电容器的底部电极形成在共同的工艺中。 电容绝缘体可以具有不同数量的子层，形成不同的材料或不同的厚度。 电容器可以形成在层间电介质层中或在金属间介电层中。 这些区域可以是混合信号区域，模拟区域，射频区域，动态随机存取存储区域等。

    Sub word line driver of a semiconductor memory device
    77.
    发明授权
    Sub word line driver of a semiconductor memory device 有权
    半导体存储器件的子字线驱动器

    公开(公告)号：US09543306B1

    公开(公告)日：2017-01-10

    申请号：US14958432

    申请日：2015-12-03

    Applicant: SK hynix Inc.

    Inventor： Han Kyu Lee

    IPC: H01L27/108 ,  H01L27/105 ,  H01L27/02 ,  H01L29/423 ,  H01L27/092

    CPC classification number: H01L27/105 ,  G11C8/08 ,  G11C8/14 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/10891 ,  H01L29/42356

    Abstract: A sub word line driver of a semiconductor memory device including a sub word line driver is disclosed. The sub word line driver of a semiconductor memory device comprising: a semiconductor substrate including an active region extended in a first direction; a plurality of gate electrodes extended in a second direction perpendicular to the active region; first and second metal contacts formed over the active region between the gate electrodes; a plurality of metal pads coupled to the first metal contacts; and a plurality of metal signal lines coupled to the second metal contacts, extended in the second direction, and bent at specific parts adjacent to the metal pads.

    Abstract translation: 公开了包括子字线驱动器的半导体存储器件的副字线驱动器。 半导体存储器件的副字线驱动器包括：半导体衬底，包括沿第一方向延伸的有源区; 多个栅电极，在垂直于有源区的第二方向上延伸; 形成在栅电极之间的有源区上的第一和第二金属触点; 耦合到所述第一金属触点的多个金属焊盘; 以及耦合到所述第二金属触点的多个金属信号线，沿所述第二方向延伸，并且在与所述金属焊盘相邻的特定部分处弯曲。

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