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    Phase-locked loop, method of operating the same, and devices having the same
    71.
    发明授权
    Phase-locked loop, method of operating the same, and devices having the same 有权
    锁相环，操作方法以及具有相同的装置

    公开(公告)号：US08981824B2

    公开(公告)日：2015-03-17

    申请号：US14201285

    申请日：2014-03-07

    申请人： Samsung Electronics Co., Ltd.

    发明人： Jae Jin Park ,  Tae Kwang Jang ,  Jenlung Liu

    IPC分类号： H03L7/06 ,  H03L7/10

    CPC分类号： H03L7/10 ,  H03L7/095 ,  H03L7/0997 ,  H03L2207/50

    摘要： A method of operating a phase-locked loop (PLL) such as an all-digital PLL includes operations of comparing a reference clock signal with a feedback signal of the PLL and outputting a comparison signal according to a result of the comparison, and detecting whether the PLL is in a lock state by using a number of times the comparison signal is toggled.

    摘要翻译： 操作诸如全数字PLL的锁相环（PLL）的方法包括将参考时钟信号与PLL的反馈信号进行比较并根据比较结果输出比较信号的操作，以及检测是否 PLL通过使用比较信号切换的次数处于锁定状态。

    METHODS AND SYSTEMS TO COMPENSATE FOR NON-LINEARITY OF A STOCHASTIC SYSTEM
    72.
    发明申请
    METHODS AND SYSTEMS TO COMPENSATE FOR NON-LINEARITY OF A STOCHASTIC SYSTEM 有权
    补偿系统非线性的方法和系统

    公开(公告)号：US20150074156A1

    公开(公告)日：2015-03-12

    申请号：US14022683

    申请日：2013-09-10

    申请人： Ofir Degani ,  Ashoke Ravi ,  Hasnain Lakdawala

    发明人： Ofir Degani ,  Ashoke Ravi ,  Hasnain Lakdawala

    IPC分类号： G06F5/00 ,  G06F17/18

    CPC分类号： G06F5/00 ,  G04F10/005 ,  H03L7/085 ,  H03L2207/50 ,  H03M1/1014 ,  H03M1/1033

    摘要： Determination of digital compensation to compensate for non-linearity of stochastic system configured to sample a phase difference, based on statistical analysis of calibration data generated by the stochastic system in response to a linear phase ramp. The stochastic system may include a set of stochastic sampler circuits to sample a phase difference at periodic events, and calibration data may include a digital value of set of stochastic samples for each of multiple events. The calibration data may include sequences of the digital values in which the digital values increment over a range of the stochastic system (i.e., between saturation states of the stochastic system). Statistical analysis may include histogram analysis to estimate the probability distribution of the calibration data. The stochastic system may be configured as part of a time-to-digital converter, which may be configured within a feedback loop of a digitally controllable phase lock loop.

    摘要翻译： 基于随机系统响应于线性相位斜坡生成的校准数据的统计分析，确定数字补偿以补偿配置为采样相位差的随机系统的非线性。 随机系统可以包括一组随机采样器电路，以在周期性事件中采样相位差，并且校准数据可以包括多个事件中的每一个的随机样本集合的数字值。 校准数据可以包括数字值的序列，其中数字值在随机系统的范围（即，随机系统的饱和状态之间）增加。 统计分析可以包括直方图分析来估计校准数据的概率分布。 随机系统可以被配置为时间 - 数字转换器的一部分，其可以配置在数字可控锁相环的反馈回路内。

    Semiconductor apparatus
    73.
    发明授权
    Semiconductor apparatus 有权
    半导体装置

    公开(公告)号：US08970268B2

    公开(公告)日：2015-03-03

    申请号：US14466191

    申请日：2014-08-22

    申请人： SK Hynix Inc.

    发明人： Kwan Dong Kim

    IPC分类号： H03L7/06 ,  H03L7/08 ,  H03L7/087

    CPC分类号： H03L7/0807 ,  H03K5/135 ,  H03K2005/00071 ,  H03L7/087 ,  H03L2207/50

    摘要： A semiconductor apparatus includes: a variable delay unit configured to delay a reference clock signal in response to a delay code and generate a data latch clock signal; a delay amount control unit configured to convert a phase of external data and a phase of the data latch clock signal into first and second codes, respectively, and generate the delay code through a calculation of the first and second codes; and a data receiver configured to latch the external data as internal data in synchronization with the data latch clock signal.

    摘要翻译： 半导体装置包括：可变延迟单元，被配置为响应延迟码延迟参考时钟信号并产生数据锁存时钟信号; 延迟量控制单元，被配置为分别将外部数据的相位和数据锁存时钟信号的相位转换为第一和第二代码，并通过第一和第二代码的计算产生延迟码; 以及数据接收器，配置为与数据锁存时钟信号同步地将外部数据锁存为内部数据。

    System clock jitter correction
    74.
    发明授权
    System clock jitter correction 有权
    系统时钟抖动校正

    公开(公告)号：US08957796B2

    公开(公告)日：2015-02-17

    申请号：US14507563

    申请日：2014-10-06

    申请人： IQ-Analog Corporation

    发明人： Mikko Waltari ,  Michael Kappes ,  William Huff

    IPC分类号： H03M1/06 ,  H03M1/12 ,  H03L7/091

    CPC分类号： H03L7/091 ,  H03L7/093 ,  H03L7/097 ,  H03L7/18 ,  H03L7/1806 ,  H03L2207/10 ,  H03L2207/50 ,  H03M1/0626 ,  H03M1/0836 ,  H03M1/12 ,  H03M1/1215 ,  H03M1/1245

    摘要： A system and method are provided for frequency multiplication jitter correction. The method accepts an analog reference signal having a first frequency, and using the analog reference signal, derives a system clock signal having a second frequency, greater than the first frequency. A PLL using a voltage controlled oscillator (VCO) is one example of a frequency multiplier. The method samples the amplitude of the analog reference signal using the system clock signal and converts the sampled analog reference signal into a digitized reference signal. In response to comparing the digitized reference signal to an ideal digitized reference signal, the phase error correction for the system clock signal is derived. The phase error correction at a first instance of time can be applied to the digitized data signal, previously converted from an analog data signal sampled at a first instance of time with the system clock signal.

    摘要翻译： 提供了一种用于倍频抖动校正的系统和方法。 该方法接受具有第一频率的模拟参考信号，并且使用模拟参考信号导出具有大于第一频率的第二频率的系统时钟信号。 使用压控振荡器（VCO）的PLL是倍频器的一个例子。 该方法使用系统时钟信号对模拟参考信号的振幅进行采样，并将采样的模拟参考信号转换为数字化参考信号。 响应于将数字化参考信号与理想数字化参考信号进行比较，导出系统时钟信号的相位误差校正。 在第一时刻的相位误差校正可以应用于数字化数据信号，该数字化数据信号是先前从系统时钟信号在第一时间采样的模拟数据信号转换的。

    FREQUENCY MULTIPLIER JITTER CORRECTION
    75.
    发明申请
    FREQUENCY MULTIPLIER JITTER CORRECTION 有权
    频率多路径抖动校正

    公开(公告)号：US20150015313A1

    公开(公告)日：2015-01-15

    申请号：US14503656

    申请日：2014-10-01

    申请人： IQ-Analog Corporation

    发明人： Mikko Waltari ,  Michael Kappes ,  William Huff

    IPC分类号： H03L7/091 ,  H03L7/097 ,  H03L7/093

    CPC分类号： H03L7/091 ,  H03L7/093 ,  H03L7/097 ,  H03L7/18 ,  H03L7/1806 ,  H03L2207/10 ,  H03L2207/50 ,  H03M1/0626 ,  H03M1/0836 ,  H03M1/12 ,  H03M1/1215 ,  H03M1/1245

    摘要： A system and method are provided for frequency multiplication jitter correction. The method accepts an analog reference signal having a first frequency, and using the analog reference signal, derives a system clock signal having a second frequency, greater than the first frequency. A PLL using a voltage controlled oscillator (VCO) is one example of a frequency multiplier. The method samples the amplitude of the analog reference signal using the system clock signal and converts the sampled analog reference signal into a digitized reference signal. In response to comparing the digitized reference signal to an ideal digitized reference signal, the phase error correction for the system clock signal is derived. The phase error correction at a first instance of time can be applied to the digitized data signal, previously converted from an analog data signal sampled at a first instance of time with the system clock signal.

    摘要翻译： 提供了一种用于倍频抖动校正的系统和方法。 该方法接受具有第一频率的模拟参考信号，并且使用模拟参考信号导出具有大于第一频率的第二频率的系统时钟信号。 使用压控振荡器（VCO）的PLL是倍频器的一个例子。 该方法使用系统时钟信号对模拟参考信号的振幅进行采样，并将采样的模拟参考信号转换为数字化参考信号。 响应于将数字化参考信号与理想数字化参考信号进行比较，导出系统时钟信号的相位误差校正。 在第一时刻的相位误差校正可以应用于数字化数据信号，该数字化数据信号是先前从系统时钟信号在第一时间采样的模拟数据信号转换的。

    DIGITAL PHASE LOCKED LOOP WITH REDUCED CONVERGENCE TIME
    76.
    发明申请
    DIGITAL PHASE LOCKED LOOP WITH REDUCED CONVERGENCE TIME 有权
    数字相位锁定时间缩短

    公开(公告)号：US20150002198A1

    公开(公告)日：2015-01-01

    申请号：US14311638

    申请日：2014-06-23

    申请人： MICROSEMI SEMICONDUCTOR ULC

    发明人： Qu Gary Jin

    IPC分类号： H03L7/093 ,  H03L7/14

    CPC分类号： H03L7/093 ,  H03L7/1075 ,  H03L2207/50

    摘要： A digital phase locked loop has a digital controlled oscillator, a phase comparator comparing the output signal of the digital controlled oscillator, or a signal derived therefrom, with a reference signal to produce a phase error signal. A loop filter produces a control signal for the digital controlled oscillator from an output of the phase comparator the loop filter. The loop filter has a proportional part producing a proportional component of the control signal, an integral part producing an integral component of the control signal, and an adder receiving the respective proportional and integral components at first and second inputs thereof to produce the control signal. The integral part includes a delayed feedback loop normally configured to accept the integral component at an input thereof. A first switch replaces the integral component at the input of the delayed feedback loop by the control signal in response to an activation signal. A control module produces the activation signal to activate the switch for brief periods when the phase error is non-zero and the rate of change of phase is less than a threshold value.

    摘要翻译： 数字锁相环具有数字控制振荡器，比较数字控制振荡器的输出信号或从其得到的信号的相位比较器与参考信号，以产生相位误差信号。 环路滤波器从相位比较器的环路滤波器的输出产生数字控制振荡器的控制信号。 环路滤波器具有比例部分，其产生控制信号的比例分量，产生控制信号的积分分量的积分部分和在其第一和第二输入处接收相应比例和积分分量的加法器，以产生控制信号。 积分部分包括通常配置为在其输入处接受积分分量的延迟反馈回路。 响应于激活信号，第一开关通过控制信号替代延迟反馈回路的输入处的积分分量。 当相位误差不为零并且相位变化率小于阈值时，控制模块产生激活信号以激活开关短暂的时间段。

    Digital phase-locked loop and phase/frequency detector module thereof
    77.
    发明授权
    Digital phase-locked loop and phase/frequency detector module thereof 有权
    数字锁相环及其相位/频率检测器模块

    公开(公告)号：US08917806B1

    公开(公告)日：2014-12-23

    申请号：US14256031

    申请日：2014-04-18

    申请人： Richtek Technology Corp

    发明人： Yen-Yin Huang ,  Kuo-Shih Tsai ,  Ming-Shih Yu

    IPC分类号： H03D3/24 ,  H04L7/033

    CPC分类号： H04L7/0331 ,  H03L2207/50

    摘要： A phase/frequency detector module, applicable to a digital phase-locked loop, includes: an edge detector for receiving a reference clock signal and a counting clock signal, where when a positive edge of the counting clock signal occurs, if a positive edge of the reference clock signal has occurred, the edge detector outputs an edge-detected signal, else the edge detector outputs an edge-not-detected signal; a counter coupled to the edge detector, where if receiving the edge-detected signal, the counter outputs a counting result forming a frequency error signal, resets, and loads a count value, and if receiving the edge-not-detected signal, the counter continues to count on the positive edge of the counting clock signal; and a frequency phase converter for performing integration over the counting result, where the integral forms a phase error signal.

    摘要翻译： 适用于数字锁相环的相位/频率检测器模块包括：边缘检测器，用于接收参考时钟信号和计数时钟信号，其中当计数时钟信号的上升沿出现时，如果 参考时钟信号发生，边缘检测器输出边沿检测信号，否则边沿检测器输出未检测到边沿的信号; 耦合到边缘检测器的计数器，其中如果接收到边沿检测信号，则计数器输出形成频率误差信号的计数结果，复位并加载计数值，并且如果接收到未被检测的边缘信号，则计数器 继续依靠计数时钟信号的上升沿; 以及用于对计数结果执行积分的频率相位转换器，其中积分形成相位误差信号。

    METHOD AND APPARATUS FOR CONTROL OF A DIGITAL PHASE LOCKED LOOP (DPLL) WITH EXPONENTIALLY SHAPED DIGITALLY CONTROLLED OSCILLATOR (DCO)
    78.
    发明申请
    METHOD AND APPARATUS FOR CONTROL OF A DIGITAL PHASE LOCKED LOOP (DPLL) WITH EXPONENTIALLY SHAPED DIGITALLY CONTROLLED OSCILLATOR (DCO) 有权
    用于控制具有指定数字控制振荡器（DCO）的数字相位锁定环（DPLL）的方法和装置

    公开(公告)号：US20140368242A1

    公开(公告)日：2014-12-18

    申请号：US13931997

    申请日：2013-06-30

    申请人： Broadcom Corporation

    发明人： Gregory Alyn Unruh

    IPC分类号： H03L7/08 ,  H03B25/00 ,  H01L25/03

    CPC分类号： H03L1/00 ,  H03L7/0995 ,  H03L7/1077 ,  H03L2207/50

    摘要： Various systems and methods utilizing a digitally controlled oscillator having frequency steps that increase in magnitude as a target output clock frequency increases are described. An integrated circuit in accordance with the disclosure includes a plurality of first transistor units fixedly coupled to an input voltage and a plurality of second transistor units switchably coupled to the first transistor units. An output coupled to the plurality of second transistor units and the plurality of first transistor units conveys an output signal having a frequency dependent on which select ones of the second transistor units are enabled. The plurality of second transistor units include a first switchable transistor unit having a transistor of a first width, a second switchable transistor unit having a transistor of a second width greater than the first width, and a third switchable transistor unit having a transistor of a third width greater than the second width.

    摘要翻译： 描述了利用数字控制振荡器的各种系统和方法，其具有以目标输出时钟频率增加的幅度增加的频率步长。 根据本公开的集成电路包括固定地耦合到输入电压的多个第一晶体管单元和可切换地耦合到第一晶体管单元的多个第二晶体管单元。 耦合到多个第二晶体管单元和多个第一晶体管单元的输出输出具有取决于第二晶体管单元中的哪一个被启用的频率的输出信号。 多个第二晶体管单元包括具有第一宽度的晶体管的第一可切换晶体管单元，具有大于第一宽度的第二宽度的晶体管的第二可切换晶体管单元和具有第三宽度的晶体管的第三可切换晶体管单元 宽度大于第二宽度。

    Fractional and integer PLL architectures
    80.
    发明授权
    Fractional and integer PLL architectures 有权
    分数和整数PLL架构

    公开(公告)号：US08890624B2

    公开(公告)日：2014-11-18

    申请号：US13645277

    申请日：2012-10-04

    申请人： QUALCOMM Incorporated

    发明人： Shuo-Wei Chen ,  David Kuochieh Su

    IPC分类号： H03L7/085 ,  H03L7/089

    CPC分类号： H03L7/0998 ,  H03K3/03 ,  H03K5/133 ,  H03K2005/00032 ,  H03K2005/00052 ,  H03L7/081 ,  H03L7/093 ,  H03L7/0991 ,  H03L7/0995 ,  H03L7/183 ,  H03L7/1974 ,  H03L2207/50

    摘要： A digital fractional PLL introduces an accumulated phase offset before the digital VCO to achieve the fractional part of the division ratio. To provide this phase offset, the digital accumulator can integrate a fractional component Δn. By forcing Δn to zero, the PLL becomes an integer-N PLL. A de-skew timing configuration can be used to remove any time mismatch between integer and fractional counters of the PLL. A digital PLL can merge the function of frequency generation (DVCO) and that of fractional frequency counting into the same circuit block by reusing various phases of the frequency output to generate a fractional frequency count. A digital integer PLL can include a comparator, wherein the feedback loop of this PLL forces the phase difference between the reference clock and feedback signals to approach zero. By changing the duty cycle of feedback signal, the frequency tracking behavior of the loop can be varied.

    摘要翻译： 数字分数PLL在数字VCO之前引入累积的相位偏移，以实现分数比的分数部分。 为了提供这种相位偏移，数字累加器可以集成分数分量＆Dgr; n。 通过强制＆Dgr; n为零，PLL变为整数N PLL。 可以使用去偏移时序配置来消除PLL的整数和分数计数器之间的任何时间不匹配。 数字PLL可以通过重新使用频率输出的各个相位来将频率产生（DVCO）的功能和分数频率计数的功能合并到相同的电路块中，以产生分数频率计数。 数字整数PLL可以包括比较器，其中该PLL的反馈环路迫使参考时钟和反馈信号之间的相位差接近零。 通过改变反馈信号的占空比，可以改变回路的频率跟踪行为。