公开(公告)号：US12062718B2

公开(公告)日：2024-08-13

申请号：US18093241

申请日：2023-01-04

申请人： Infineon Technologies Austria AG

发明人： Gerhard Noebauer

IPC分类号： H01L29/78 ,  G01R19/00 ,  H01L29/06 ,  H01L29/08 ,  H01L29/40

CPC分类号： H01L29/7815 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/402 ,  H01L29/407 ,  H01L29/7813 ,  G01R19/0092

摘要： A transistor arrangement includes a drift and drain region arranged in a semiconductor body and each connected to a drain node, a plurality of load transistor cells each comprising a source region integrated in a first region of the semiconductor body, a plurality of sense transistor cells each comprising a source region integrated in a second region of the semiconductor body, a first source node electrically connected to the source region of each of the plurality of the load transistor cells via a first source conductor, and a second source node electrically connected to the source region of each of the plurality of the sense transistor cells via a second source conductor, and wherein a resistance of the second source conductor is different from a resistance of the first source conductor.

公开(公告)号：US20240266439A1

公开(公告)日：2024-08-08

申请号：US18637874

申请日：2024-04-17

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chun-Chieh WANG ,  Yu-Ting LIN ,  Yueh-Ching PAI ,  Shih-Chieh CHANG ,  Huai-Tei YANG

IPC分类号： H01L29/78 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/32 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66

CPC分类号： H01L29/7856 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/3065 ,  H01L21/3105 ,  H01L21/31116 ,  H01L21/32 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/66803 ,  H01L21/823814 ,  H01L29/66545

摘要： A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure formed over a fin structure, and a gate spacer layer formed on a sidewall surface of the gate structure. The semiconductor structure includes a source/drain (S/D) epitaxial layer formed adjacent to the gate structure, and a dielectric spacer layer formed on the S/D epitaxial layer. The semiconductor structure includes a contact plug barrier formed over the S/D epitaxial layer, and a contact plug surrounding by the contact plug barrier, wherein the contact plug is separated from the gate spacer layer by the dielectric spacer layer and the contact plug barrier.

公开(公告)号：US20240266396A1

公开(公告)日：2024-08-08

申请号：US18164399

申请日：2023-02-03

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kuan-Ting PAN ,  Che-Lun CHANG ,  Kuo-Cheng CHIANG ,  Chih-Hao WANG

IPC分类号： H01L29/06 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC分类号： H01L29/0673 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823481 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/78696

摘要： A semiconductor structure and a method for forming the same are provided. The semiconductor device structure includes a substrate having a first region and a second region, and a plurality of first nanostructures stacked in a vertical direction in the first region. The semiconductor device structure includes a plurality of second nanostructures stacked in the vertical direction in the second region, and a silicon germanium (SiGe) layer formed below the first nanostructures in the first region. The semiconductor device structure also includes a first gate structure surrounding the first nanostructures in the first region, and a second gate structure surrounding the second nanostructures in the second region. The bottommost surface of the second gate structure is lower than the bottommost surface of the first gate structure.

公开(公告)号：US12058907B2

公开(公告)日：2024-08-06

申请号：US18158320

申请日：2023-01-23

申请人： SAMSUNG DISPLAY CO., LTD.

发明人： Hyun Min Cho ,  Tae Wook Kang ,  Sang Gun Choi ,  Shin Il Choi ,  Yun Jung Oh ,  Myoung Geun Cha

IPC分类号： H01L29/08 ,  H10K50/824 ,  H10K59/121 ,  H10K59/124 ,  H10K59/131 ,  H10K71/00

CPC分类号： H10K59/131 ,  H10K50/824 ,  H10K59/1213 ,  H10K59/124 ,  H10K71/00

摘要： A display apparatus includes: a base substrate; a thin film transistor and a power supply wire on the base substrate; a first electrode on the base substrate, and electrically connected to the thin film transistor; a light emitting layer and a common layer on the first electrode; and a second electrode on the common layer. The power supply wire includes: a first conductive layer; a second conductive layer on the first conductive layer; and a third conductive layer on the second conductive layer. The third conductive layer protrudes more than the second conductive layer on a side surface of the power supply wire, and the second electrode contacts a side surface of the second conductive layer.

公开(公告)号：US12057495B2

公开(公告)日：2024-08-06

申请号：US18326682

申请日：2023-05-31

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Yao-Sheng Huang ,  Hung-Chang Sun ,  I-Ming Chang ,  Zi-Wei Fang

IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L21/311 ,  H01L29/08 ,  H01L29/78 ,  H01L21/306

CPC分类号： H01L29/66795 ,  H01L21/02488 ,  H01L21/02513 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02598 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02661 ,  H01L21/02675 ,  H01L21/31116 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/785 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/30604

摘要： A semiconductor device includes a semiconductor fin, a gate structure, a doped semiconductor layer, and a dielectric structure. The semiconductor fin has a top portion and a lower portion extending from the top portion to a substrate. The gate structure extends across the semiconductor fin. The doped semiconductor layer interfaces the top portion of the semiconductor fin. In a cross-section taken along a lengthwise direction of the gate structure, the doped semiconductor layer has an outer profile conformal to a profile of the top portion of the semiconductor fin.

公开(公告)号：US20240258427A1

公开(公告)日：2024-08-01

申请号：US18605406

申请日：2024-03-14

申请人： Intel Corporation

发明人： Ryan KEECH ,  Benjamin CHU-KUNG ,  Subrina RAFIQUE ,  Devin MERRILL ,  Ashish AGRAWAL ,  Harold KENNEL ,  Yang CAO ,  Dipanjan BASU ,  Jessica TORRES ,  Anand MURTHY

IPC分类号： H01L29/78 ,  H01L21/02 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L29/167 ,  H01L29/45 ,  H01L29/66

CPC分类号： H01L29/7848 ,  H01L21/02532 ,  H01L21/02579 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/167 ,  H01L29/45 ,  H01L29/66515 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

摘要： Integrated circuit structures having source or drain structures and germanium N-channels are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion, the upper fin portion including germanium. A gate stack is over the upper fin portion of the fin. A first source or drain structure includes an epitaxial structure embedded in the fin at a first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at a second side of the gate stack. Each epitaxial structure includes a first semiconductor layer in contact with the upper fin portion, and a second semiconductor layer on the first semiconductor layer. The first semiconductor layer comprises silicon, germanium and phosphorous, and the second semiconductor layer comprises silicon and phosphorous.

公开(公告)号：US20240258387A1

公开(公告)日：2024-08-01

申请号：US18314446

申请日：2023-05-09

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yi-Syuan Siao ,  Meng-Han Chou ,  Chien-Yu Lin ,  Wei-Ting Chang ,  Tien-Shun Chang ,  Chin-I Kuan ,  Su-Hao Liu ,  Chi On Chui

IPC分类号： H01L29/417 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC分类号： H01L29/41733 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696

摘要： In an embodiment, a device includes: a first semiconductor nanostructure; a second semiconductor nanostructure adjacent the first semiconductor nanostructure; a first source/drain region on a first sidewall of the first semiconductor nanostructure; a second source/drain region on a second sidewall of the second semiconductor nanostructure, the second source/drain region completely separated from the first source/drain region; and a source/drain contact between the first source/drain region and the second source/drain region.

公开(公告)号：US20240258373A1

公开(公告)日：2024-08-01

申请号：US18162854

申请日：2023-02-01

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ta-Yuan Kung ,  Chen-Liang Chu ,  Chih-Wen Albert Yao ,  Fei-Yun Chen ,  Ming-Ta Lei ,  Ruey-Hsin Liu ,  Yu-Chang Jong

IPC分类号： H01L29/08 ,  H01L21/302 ,  H01L29/06 ,  H01L29/40 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/0847 ,  H01L21/302 ,  H01L29/0692 ,  H01L29/402 ,  H01L29/4983 ,  H01L29/66689 ,  H01L29/7833

摘要： An integrated chip including a first source/drain region and a second source/drain region in a semiconductor substrate and laterally spaced apart along a top surface of the substrate. A gate dielectric layer is over the substrate and extends laterally between the first source/drain region and the second source/drain region. A thickness of the gate dielectric layer along a first sidewall of the gate dielectric layer is less than an average thickness of the gate dielectric layer. A trench isolation layer extends along gate dielectric layer. A first sidewall of the trench isolation layer extends along the first sidewall of the gate dielectric layer. A gate layer is directly over the gate dielectric layer and between the first source/drain region and the second source/drain region. A first sidewall of the gate layer is directly over the gate dielectric layer and laterally setback from the first sidewall of the gate dielectric layer.

公开(公告)号：US20240251537A1

公开(公告)日：2024-07-25

申请号：US18428994

申请日：2024-01-31

申请人： Taiwan Semiconductor Manufacturing Co., Ltd

发明人： Dian-Sheg Yu ,  Ren-Fen Tsui ,  Jhon Jhy Liaw

IPC分类号： H10B10/00 ,  H01L21/265 ,  H01L21/306 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/092 ,  H01L29/08 ,  H01L29/66

CPC分类号： H10B10/12 ,  H01L21/26513 ,  H01L21/30604 ,  H01L21/76802 ,  H01L21/823418 ,  H01L21/823475 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823864 ,  H01L21/823871 ,  H01L27/0203 ,  H01L29/0847 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66636 ,  H01L21/76814 ,  H01L21/76897 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/0928 ,  H10B10/18

摘要： A method includes forming a first transistor including forming a first gate stack, epitaxially growing a first source/drain region on a side of the first gate stack, and performing a first implantation to implant the first source/drain region. The method further includes forming a second transistor including forming a second gate stack, forming a second gate spacer on a sidewall of the second gate stack, epitaxially growing a second source/drain region on a side of the second gate stack, and performing a second implantation to implant the second source/drain region. An inter-layer dielectric is formed to cover the first source/drain region and the second source/drain region. The first implantation is performed before the inter-layer dielectric is formed, and the second implantation is performed after the inter-layer dielectric is formed.

公开(公告)号：US20240250167A1

公开(公告)日：2024-07-25

申请号：US18625430

申请日：2024-04-03

申请人： FUJI ELECTRIC CO., LTD.

发明人： Keiji OKUMURA

IPC分类号： H01L29/78 ,  H01L21/04 ,  H01L29/08 ,  H01L29/10 ,  H01L29/16 ,  H01L29/36 ,  H01L29/423 ,  H01L29/66

CPC分类号： H01L29/7813 ,  H01L21/046 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/66068 ,  H01L29/7811 ,  H01L29/36

摘要： A semiconductor device includes a current spreading region of the first conductivity type provided on a drift layer and having a higher impurity density than the drift layer; a base region of a second conductivity type provided on the current spreading region; a base contact region of the second conductivity type provided in a top part of the base region and having a higher impurity density than the base region; and an electrode contact region of the first conductivity type provided in a top part of the base region that is laterally in contact with the base contact region, the electrode contact region having a higher impurity density than the drift layer, wherein a density of a second conductivity type impurity element in the base contact region is at least two times as much as a density of a first conductivity type impurity element in the electrode contact region.