公开(公告)号：US10014047B2

公开(公告)日：2018-07-03

申请号：US15610001

申请日：2017-05-31

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Kenneth L. Wright

IPC: G11C7/10 ,  G11C11/4093 ,  G11C11/4096 ,  G11C29/52

CPC classification number: G11C11/4093 ,  G06F11/1048 ,  G11C7/02 ,  G11C11/4096 ,  G11C29/52 ,  G11C2029/0411

Abstract: Described are memory modules that support different error detection and correction (EDC) schemes in both single- and multiple-module memory systems. The memory modules are width configurable, and support the different EDC schemes for relatively wide and narrow module data widths. Data buffers on the modules support the half-width and full-width modes, and also support time-division-multiplexing to access additional memory components on each module in support of enhanced EDC.

公开(公告)号：US20180174624A1

公开(公告)日：2018-06-21

申请号：US15837475

申请日：2017-12-11

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely K. Tsern

IPC: G11C7/10

CPC classification number: G11C7/1066 ,  G11C7/10 ,  G11C7/1072

Abstract: A memory component includes a memory bank comprising a plurality of storage cells and a data interface block configured to transfer data between the memory component and a component external to the memory component. The memory component further includes a plurality of column interface buses coupled between the memory bank and the data interface block, wherein a first column interface bus of the plurality of column interface buses is configured to transfer data between a first storage cell of the plurality of storage cells and the data interface block during a first access operation and wherein a second column interface bus of the plurality of column interface buses is configured to transfer the data between the first storage cell and the data interface block during a second access operation.

公开(公告)号：US20180168070A1

公开(公告)日：2018-06-14

申请号：US15783949

申请日：2017-10-13

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Carl W. Werner

IPC: H05K7/20 ,  G06F1/20 ,  H01B7/04 ,  G06F1/18 ,  H01B7/29 ,  H01L27/108

CPC classification number: H05K7/20372 ,  G06F1/18 ,  G06F1/20 ,  G06F1/206 ,  H01B1/026 ,  H01B3/12 ,  H01B7/04 ,  H01B7/29 ,  H01L23/3677 ,  H01L23/49888 ,  H01L23/522 ,  H01L23/53285 ,  H01L23/5387 ,  H01L27/108

Abstract: The embodiments herein describe technologies of cryogenic digital systems with a first component located in a first cryogenic temperature domain and a second component located in a second cryogenic temperature domain that is lower in temperature than the first cryogenic temperature domain. An electrical conductor is coupled between the first component and the second component along a first plane. The electrical conductor carries a signal between the first component and the second component. A cooling assembly is coupled to a segment of the electrical conductor. The cooling assembly may include an electrical insulator including ceramic material. The cooling assembly may include a cold plate, two cold plates, or an orthogonal cold strip.

公开(公告)号：US20180166118A1

公开(公告)日：2018-06-14

申请号：US15805009

申请日：2017-11-06

Applicant: Rambus Inc.

Inventor： Frederick A. Ware

IPC: G11C11/4076 ,  G11C7/10 ,  G11C11/409 ,  G06F1/10 ,  G06F13/16 ,  G06F13/42 ,  G11C7/22 ,  G11C8/18

CPC classification number: G11C11/4076 ,  G06F1/10 ,  G06F13/1689 ,  G06F13/4243 ,  G11C7/1072 ,  G11C7/22 ,  G11C8/18 ,  G11C11/409 ,  G11C2207/2254

Abstract: A clock signal is transmitted to first and second integrated circuit (IC) components via a clock signal line, the clock signal having a first arrival time at the first IC component and a second, later arrival time at the second IC component. A write command is transmitted to the first and second IC components to be sampled by those components at respective times corresponding to transitions of the clock signal, and write data is transmitted to the first and second IC components in association with the write command. First and second strobe signals are transmitted to the first and second IC components, respectively, to time reception of the first and second write data in those components. The first and second strobe signals are selected from a plurality of phase-offset timing signals to compensate for respective timing skews between the clock signal and the first and second strobe signals.

公开(公告)号：US20180143873A1

公开(公告)日：2018-05-24

申请号：US15829682

申请日：2017-12-01

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely Tsern

IPC: G06F11/10 ,  H03M13/15 ,  G11C29/44 ,  G06F11/16 ,  G11C29/00 ,  G11C29/52 ,  G11C29/42 ,  G11C7/10 ,  G06F11/20

CPC classification number: G06F11/1044 ,  G06F11/1048 ,  G06F11/1068 ,  G06F11/1666 ,  G06F11/20 ,  G11C7/10 ,  G11C29/42 ,  G11C29/4401 ,  G11C29/52 ,  G11C29/70 ,  G11C29/765 ,  G11C2029/4402 ,  H03M13/1575

Abstract: A memory module is disclosed that includes a substrate, a memory device that outputs read data, and a buffer. The buffer has a primary interface for transferring the read data to a memory controller and a secondary interface coupled to the memory device to receive the read data. The buffer includes error logic to identify an error in the received read data and to identify a storage cell location in the memory device associated with the error. Repair logic maps a replacement storage element as a substitute storage element for the storage cell location associated with the error.

公开(公告)号：US09933960B2

公开(公告)日：2018-04-03

申请号：US15253736

申请日：2016-08-31

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Robert E. Palmer ,  John W. Poulton

IPC: G06F12/00 ,  G06F13/00 ,  G06F3/06 ,  G06F13/16 ,  G06Q10/00 ,  G06Q20/00 ,  G11C7/02 ,  G11C11/406

CPC classification number: G06F3/0619 ,  G06F3/0629 ,  G06F3/0659 ,  G06F3/0673 ,  G06F13/1636 ,  G06F13/1689 ,  G06Q10/00 ,  G06Q20/00 ,  G11C7/02 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/40615 ,  G11C11/40618 ,  G11C2211/4061

Abstract: A system includes a memory controller and a memory device having a command interface and a plurality of memory banks, each with a plurality of rows of memory cells. The memory controller transmits an auto-refresh command to the memory device. Responsive to the auto-refresh command, during a first time interval, the memory device performs refresh operations to refresh the memory cells and the command interface of the memory device is placed into a calibration mode for the duration of the first time interval. Concurrently, during at least a portion of the first time interval, the memory controller performs a calibration of the command interface of the memory device. The auto-refresh command may specify an order in which memory banks of the memory device are to be refreshed, such that the memory device sequentially refreshes a respective row in the plurality of memory banks in the specified bank order.

公开(公告)号：US20180090187A1

公开(公告)日：2018-03-29

申请号：US15721755

申请日：2017-09-30

Applicant: Rambus Inc.

Inventor： Scott C. Best ,  Frederick A. Ware ,  William N. Ng

IPC: G11C7/10 ,  G11C5/04

Abstract: A memory module can be programmed to deliver relatively wide, low-latency data in a first access mode, or to sacrifice some latency in return for a narrower data width, a narrower command width, or both, in a second access mode. The narrow, higher-latency mode requires fewer connections and traces. A controller can therefore support more modules, and thus increased system capacity. Programmable modules thus allow computer manufacturers to strike a desired balance between memory latency, capacity, and cost.

公开(公告)号：US20180067538A1

公开(公告)日：2018-03-08

申请号：US15682257

申请日：2017-08-21

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Robert E. Palmer ,  John W. Poulton ,  Andrew M. Fuller

IPC: G06F1/32 ,  G11C7/10 ,  G06F3/06 ,  G11C11/4096 ,  G11C11/4076 ,  G11C7/22 ,  G06F1/12 ,  G11C7/04 ,  G06F13/16 ,  G06F9/38 ,  G06F13/36

CPC classification number: G06F1/3237 ,  G06F1/12 ,  G06F1/3225 ,  G06F1/324 ,  G06F3/0604 ,  G06F3/0625 ,  G06F3/0629 ,  G06F3/0673 ,  G06F9/3836 ,  G06F12/0857 ,  G06F13/1689 ,  G06F13/36 ,  G06F2201/88 ,  G11C7/04 ,  G11C7/10 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/109 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C11/4076 ,  G11C11/4096 ,  G11C2207/2254 ,  Y02D10/14

Abstract: A memory controller component of a memory system stores memory access requests within a transaction queue until serviced so that, over time, the transaction queue alternates between occupied and empty states. The memory controller transitions the memory system to a low power mode in response to detecting the transaction queue is has remained in the empty state for a predetermined time. In the transition to the low power mode, the memory controller disables oscillation of one or more timing signals required to time data signaling operations within synchronous communication circuits of one or more attached memory devices and also disables one or more power consuming circuits within the synchronous communication circuits of the one or more memory devices.

公开(公告)号：US09875787B2

公开(公告)日：2018-01-23

申请号：US15352366

申请日：2016-11-15

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Thomas Vogelsang

IPC: G11C7/10 ,  G11C11/4093 ,  G11C11/4094 ,  G11C11/4076

CPC classification number: G11C11/4093 ,  G11C11/4076 ,  G11C11/4094 ,  G11C11/4097

Abstract: A memory stack comprises at least two memory components. The memory components have a first data link interface and are to transmit signals on a data link coupled to the first data link interface at a first voltage level. A buffer component has a second data link interface coupled to the data link. The buffer component is to receive signals on the second data link interface at the first voltage level. A level shifting latch produces a second voltage level in response to receiving the signals at the second data link interface, where the second voltage level is higher than the first voltage level.

公开(公告)号：US20180012644A1

公开(公告)日：2018-01-11

申请号：US15666496

申请日：2017-08-01

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely K. Tsern ,  Richard E. Perego ,  Craig E. Hampel

IPC: G11C11/4076 ,  G06F1/06 ,  G11C29/02 ,  G11C11/4096 ,  G11C11/409 ,  G11C8/18 ,  G11C7/22 ,  G11C7/10 ,  G11C5/06 ,  G06F13/40 ,  G06F13/16 ,  G06F3/06 ,  G06F1/12 ,  G06F1/10 ,  G11C29/50 ,  G11C7/04

CPC classification number: G11C11/4076 ,  G06F1/06 ,  G06F1/105 ,  G06F1/12 ,  G06F3/0604 ,  G06F3/0658 ,  G06F3/0673 ,  G06F13/1684 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/4086 ,  G11C5/063 ,  G11C7/04 ,  G11C7/1051 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/22 ,  G11C7/222 ,  G11C8/18 ,  G11C11/409 ,  G11C11/4096 ,  G11C29/02 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50008 ,  G11C29/50012

Abstract: A memory controller component includes transmit circuitry and adjusting circuitry. The transmit circuitry transmits a clock signal and write data to a DRAM, the write data to be sampled by the DRAM using a timing signal. The adjusting circuitry adjusts transmit timing of the write data and of the timing signal such that an edge transition of the timing signal is aligned with an edge transition of the clock signal at the DRAM.