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    Depletion-free MOS using atomic-layer doping
    83.
    发明授权
    Depletion-free MOS using atomic-layer doping 有权
    使用原子层掺杂的无耗氧MOS

    公开(公告)号：US07790535B2

    公开(公告)日：2010-09-07

    申请号：US12211546

    申请日：2008-09-16

    Applicant: Jing-Cheng Lin ,  Chen-Hua Yu

    Inventor： Jing-Cheng Lin ,  Chen-Hua Yu

    IPC: H01L21/20

    CPC classification number: H01L21/823842 ,  H01L21/2254 ,  H01L21/28035 ,  H01L29/4925 ,  H01L29/6659

    Abstract: A semiconductor device and a method of manufacturing are provided. A dielectric layer is formed over a substrate, and a first silicon-containing layer, undoped, is formed over the dielectric layer. Atomic-layer doping is used to dope the undoped silicon-containing layer. A second silicon-containing layer is formed over first silicon-containing layer. The process may be expanded to include forming a PMOS and NMOS device on the same wafer. For example, the first silicon-containing layer may be thinned in the PMOS region prior to the atomic-layer doping. In the NMOS region, the doped portion of the first silicon-containing layer is removed such that the remaining portion of the first silicon-containing layer in the NMOS is undoped. Thereafter, another atomic-layer doping process may be used to dope the first silicon-containing layer in the NMOS region to a different conductivity type. A third silicon-containing layer may be formed doped to the respective conductivity type.

    Abstract translation: 提供半导体器件和制造方法。 介电层形成在衬底上，并且在介电层上形成未掺杂的第一含硅层。 原子层掺杂用于掺杂未掺杂的含硅层。 在第一含硅层上形成第二含硅层。 该过程可以扩展到包括在同一晶片上形成PMOS和NMOS器件。 例如，在原子层掺杂之前，第一含硅层可以在PMOS区中减薄。 在NMOS区域中，去除第一含硅层的掺杂部分，使得NMOS中的第一含硅层的剩余部分未掺杂。 此后，可以使用另一种原子层掺杂工艺将NMOS区域中的第一含硅层掺杂到不同的导电类型。 可以形成掺杂到相应导电类型的第三含硅层。

    Methods for Forming NMOS and PMOS Devices on Germanium-Based Substrates
    84.
    发明申请
    Methods for Forming NMOS and PMOS Devices on Germanium-Based Substrates 审中-公开
    在锗基底板上形成NMOS和PMOS器件的方法

    公开(公告)号：US20100181626A1

    公开(公告)日：2010-07-22

    申请号：US12617026

    申请日：2009-11-12

    Applicant: Jing-Cheng Lin ,  Chen-Hua Yu

    Inventor： Jing-Cheng Lin ,  Chen-Hua Yu

    IPC: H01L27/092

    CPC classification number: H01L21/823807 ,  H01L21/823412 ,  H01L21/823814 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/092

    Abstract: A semiconductor structure includes a germanium substrate having a first region and a second region. A first silicon cap is over the first region of the germanium substrate. A second silicon cap is over the second region of the germanium substrate, wherein a first thickness of the first silicon cap is less than a second thickness of the second silicon cap. A PMOS device includes a first gate dielectric over the first silicon cap. An NMOS device includes a second gate dielectric over the second silicon cap.

    Abstract translation: 半导体结构包括具有第一区域和第二区域的锗衬底。 第一硅帽位于锗衬底的第一区域之上。 第二硅帽位于锗衬底的第二区域之上，其中第一硅帽的第一厚度小于第二硅帽的第二厚度。 PMOS器件包括在第一硅帽上的第一栅极电介质。 NMOS器件包括位于第二硅帽上的第二栅极电介质。

    Method for forming composite barrier layer
    85.
    发明申请
    Method for forming composite barrier layer 有权
    形成复合阻挡层的方法

    公开(公告)号：US20090047780A1

    公开(公告)日：2009-02-19

    申请号：US12287516

    申请日：2008-10-10

    Applicant: Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Hsien-Ming Lee ,  Shing-Chyang Pan ,  Chao-Hsien Peng ,  Li-Lin Su ,  Jing-Cheng Lin ,  Shao-Lin Shue ,  Mong-Song Liang

    Inventor： Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Hsien-Ming Lee ,  Shing-Chyang Pan ,  Chao-Hsien Peng ,  Li-Lin Su ,  Jing-Cheng Lin ,  Shao-Lin Shue ,  Mong-Song Liang

    IPC: H01L21/44

    CPC classification number: H01L21/76844 ,  H01L21/76846 ,  H01L21/76862 ,  Y10S438/927

    Abstract: Provided is a method for forming a composite barrier layer with superior barrier qualities and superior adhesion properties to both dielectric materials and conductive materials as the composite barrier layer extends throughout the semiconductor device. The composite barrier layer may be formed in regions where it is disposed between two conductive layers and in regions where it is disposed between a conductive layer and a dielectric material. The composite barrier layer may consist of various pluralities of layers and the arrangement of layers that form the composite barrier layer may differ as the barrier layer extends throughout different sections of the device. Amorphous layers of the composite barrier layer generally form boundaries with dielectric materials and crystalline layers generally form boundaries with conductive materials such as interconnect materials.

    Abstract translation: 提供了一种形成复合阻挡层的方法，该复合阻挡层具有优异的阻挡性能，并且当复合阻挡层贯穿整个半导体器件时，两种电介质材料和导电材料具有优异的粘合性能。 复合阻挡层可以形成在其设置在两个导电层之间的区域中，并且在其布置在导电层和电介质材料之间的区域中。 复合阻挡层可以由各种多个层组成，并且形成复合阻挡层的层的布置可以随着阻挡层在装置的不同部分延伸而不同。 复合阻挡层的非晶层通常与电介质材料形成边界，并且结晶层通常与诸如互连材料的导电材料形成边界。

    Adhesion of copper and etch stop layer for copper alloy
    86.
    发明授权
    Adhesion of copper and etch stop layer for copper alloy 有权
    铜合金的附着力和蚀刻停止层

    公开(公告)号：US07443029B2

    公开(公告)日：2008-10-28

    申请号：US11201845

    申请日：2005-08-11

    Applicant: Jing Cheng Lin ,  Ching-Hua Hsieh ,  Shau-Lin Shue ,  Mong-Song Liang

    Inventor： Jing Cheng Lin ,  Ching-Hua Hsieh ,  Shau-Lin Shue ,  Mong-Song Liang

    IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC classification number: H01L21/76843 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76855 ,  H01L21/76864 ,  H01L21/76873 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A new method and structure is provided for the creation of a copper dual damascene interconnect. A dual damascene structure is created in the layer of dielectric, optionally a metal barrier layer is deposited over exposed surfaces of the dual damascene structure. A copper seed layer is deposited, the dual damascene structure is filled with copper. An anneal is applied to the created copper interconnect after which excess copper is removed from the dielectric. Of critical importance to the invention, a thin layer of oxide is then deposited as a cap layer over the copper dual damascene interconnect, an etch stop layer is then deposited over the thin layer of oxide for continued upper-level metallization.

    Abstract translation: 提供了一种新的方法和结构，用于创建铜双镶嵌互连。 在电介质层中产生双镶嵌结构，任选地，金属阻挡层沉积在双镶嵌结构的暴露表面上。 沉积铜籽晶层，双镶嵌结构填充铜。 对所制造的铜互连进行退火，之后从电介质去除多余的铜。 对本发明至关重要的是，然后在铜双镶嵌互连件上沉积薄层的氧化物作为覆盖层，然后将蚀刻停止层沉积在氧化物薄层上用于持续的上层金属化。

    Prediction and control of NBTI of Integrated circuits
    87.
    发明申请
    Prediction and control of NBTI of Integrated circuits 有权
    集成电路NBTI的预测与控制

    公开(公告)号：US20080071511A1

    公开(公告)日：2008-03-20

    申请号：US11800623

    申请日：2007-05-07

    Applicant: Jing-Cheng Lin

    Inventor： Jing-Cheng Lin

    IPC: G06F17/50

    CPC classification number: G06F17/5036

    Abstract: A modeling system for modeling integrated circuits includes a process variation generator for generating a first statistic distribution of a process parameter; a performance parameter distribution generator for generating a second distribution of a performance parameter; a stress generator for generating a third statistic distribution of the performance parameter under a stress condition; and a circuit simulator for receiving data randomly generated based on the first, the second and the third distributions and for generating a statistic distribution of a target performance parameter.

    Abstract translation: 用于对集成电路进行建模的建模系统包括用于生成过程参数的第一统计分布的过程变化发生器; 性能参数分配生成器，用于生成性能参数的第二分布; 应力发生器，用于在应力条件下产生所述性能参数的第三统计分布; 以及电路模拟器，用于接收基于第一，第二和第三分布随机生成的数据，并用于生成目标性能参数的统计分布。

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