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    Circuit board and method for manufaturing thereof
    81.
    发明申请
    Circuit board and method for manufaturing thereof 有权
    电路板及其制造方法

    公开(公告)号：US20080264676A1

    公开(公告)日：2008-10-30

    申请号：US11976207

    申请日：2007-10-22

    Applicant: Shuhichi Okabe ,  Myung-Sam Kang ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Jeong-Woo Park ,  Ji-Eun Kim

    Inventor： Shuhichi Okabe ,  Myung-Sam Kang ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Jeong-Woo Park ,  Ji-Eun Kim

    IPC: H05K1/00

    CPC classification number: H05K1/0265 ,  H05K1/116 ,  H05K3/107 ,  H05K3/108 ,  H05K3/205 ,  H05K3/421 ,  H05K2201/0379 ,  H05K2201/0394 ,  H05K2201/09509 ,  H05K2201/09736 ,  H05K2203/0361

    Abstract: A method of manufacturing a circuit board that includes: forming a conductive relievo pattern, including a first plating layer, a first metal layer, and a second plating layer stacked sequentially in correspondence with a first circuit pattern, on a seed layer stacked on a carrier; stacking and pressing together the carrier and an insulator, such that a surface of the carrier having the conductive relievo pattern faces the insulator; transcribing the conductive relievo pattern into the insulator by removing the carrier; forming a conduction pattern, including a third plating layer and a second metal layer stacked sequentially in correspondence with a second circuit pattern, on the surface of the insulator having the conductive relievo pattern transcribed; removing the first plating layer and seed layer; and removing the first and second metal layers, can provide a circuit board that has high-density circuit patterns without an increased amount of insulator.

    Abstract translation: 一种电路板的制造方法，其特征在于，包括：在堆叠在载体上的种子层上，形成导电消除图案，所述导电解像图案包括依次与第一电路图案对应地层叠的第一镀层，第一金属层和第二镀层 ; 将载体和绝缘体堆叠并压在一起，使得具有导电缓冲图案的载体的表面面向绝缘体; 通过移除载体将导电释放图案转印到绝缘体中; 在具有转印的导电消除图案的绝缘体的表面上形成包括与第二电路图案顺序堆叠的第三镀层和第二金属层的导电图案; 去除第一镀层和籽晶层; 并且去除第一和第二金属层可以提供具有高密度电路图案而不增加绝缘体量的电路板。

    Method for manufacturing circuit board
    82.
    发明申请
    Method for manufacturing circuit board 审中-公开
    电路板制造方法

    公开(公告)号：US20080251494A1

    公开(公告)日：2008-10-16

    申请号：US12078058

    申请日：2008-03-26

    Applicant: Jung-Hyun Park ,  Byoung-Youl Min ,  Jeong-Woo Park ,  Jong-Gyu Choi ,  Ji-Eun Kim ,  Myung-Sam Kang

    Inventor： Jung-Hyun Park ,  Byoung-Youl Min ,  Jeong-Woo Park ,  Jong-Gyu Choi ,  Ji-Eun Kim ,  Myung-Sam Kang

    IPC: H01B13/00 ,  C25D5/34

    CPC classification number: C25D7/123 ,  H05K3/0038 ,  H05K3/108 ,  H05K3/205 ,  H05K3/421 ,  H05K3/423 ,  H05K2201/0376 ,  H05K2201/0394 ,  H05K2201/09563 ,  H05K2203/108

    Abstract: A method of manufacturing a circuit board is disclosed. The method may include: forming a relievo pattern, which is in a corresponding relationship with a circuit pattern, on a metal layer that is stacked on a carrier; stacking and pressing the carrier onto an insulation layer with the relievo pattern facing the insulation layer; transcribing the metal layer and the relievo pattern into the insulation layer by removing the carrier; forming a via hole in the insulation layer on which the metal layer is transcribed; and filling the via hole and forming a plating layer over the metal layer by performing plating over the insulation layer on which the metal layer is transcribed. As the relievo pattern may be formed on the metal layer stacked on the carrier, and the relievo pattern may be transcribed into the insulation layer, high-density circuit patterns can be formed.

    Abstract translation: 公开了一种制造电路板的方法。 该方法可以包括：在层叠在载体上的金属层上形成与电路图案对应关系的释放图案; 将载体堆叠并压制到绝缘层上，其中减震图案面向绝缘层; 通过移除载体将金属层和释放图案转印到绝缘层中; 在所述绝缘层上形成通孔，所述绝缘层中所述金属层被转录到所述绝缘层上; 并通过在其上转印有金属层的绝缘层上进行电镀来填充通孔并在金属层上形成镀层。 由于可以在堆叠在载体上的金属层上形成缓和图案，并且可以将缓冲图案转录到绝缘层中，可以形成高密度电路图案。

    Method of manufacturing printed circuit board
    83.
    发明申请
    Method of manufacturing printed circuit board 审中-公开
    制造印刷电路板的方法

    公开(公告)号：US20080115355A1

    公开(公告)日：2008-05-22

    申请号：US11984209

    申请日：2007-11-14

    Applicant: Jung-Hyun Park ,  Byoung-Youl Min ,  Je-Gwang Yoo ,  Myung-Sam Kang

    Inventor： Jung-Hyun Park ,  Byoung-Youl Min ,  Je-Gwang Yoo ,  Myung-Sam Kang

    IPC: H05K3/10 ,  H01K3/10

    CPC classification number: H05K3/421 ,  H05K1/115 ,  H05K3/205 ,  H05K2201/0394 ,  H05K2201/09545 ,  H05K2201/09563 ,  H05K2203/0353 ,  H05K2203/0542 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49165

    Abstract: A method of manufacturing a printed circuit board is disclosed. Using the method, which includes embedding a first circuit pattern and a second circuit pattern in one side and the other side of an insulation substrate, forming a via hole by removing portions of the insulation substrate and the first circuit pattern, and electrically connecting the first circuit pattern and the second circuit pattern by forming a plating layer in the via hole, it is possible to form high-density circuits, as circuitry may be formed in portions that might have been occupied by lands, and more circuitry may be implemented for a given area of insulation substrate, whereby a fine-patterned printed circuit board may be implemented that has a high degree of integration. Also, a printed circuit board can be produced which allows good signal transfers between layers and with which fine circuit patterns can be implemented with inexpensive costs.

    Abstract translation: 公开了一种制造印刷电路板的方法。 使用该方法，其包括在绝缘基板的一侧和另一侧嵌入第一电路图案和第二电路图案，通过去除绝缘基板和第一电路图案的部分而形成通孔，并且将第一 电路图案和第二电路图案，通过在通孔中形成镀层，可以形成高密度电路，因为电路可以形成为可能已经被焊盘占据的部分，并且可以实现更多的电路用于 可以实现具有高度集成度的精细图案化印刷电路板。 此外，可以制造印刷电路板，其可以在层之间进行良好的信号传输，并且可以以廉价的成本实现精细的电路图案。

    Method of manufacturing a memory device
    85.
    发明申请
    Method of manufacturing a memory device 审中-公开
    制造存储器件的方法

    公开(公告)号：US20080014729A1

    公开(公告)日：2008-01-17

    申请号：US11820516

    申请日：2007-06-20

    Applicant: Woong Lee ,  Jung-Geun Jee ,  Hyoeng-Ki Kim ,  Jung-Hyun Park ,  Ho-Min Son ,  Won-Jun Jang

    Inventor： Woong Lee ,  Jung-Geun Jee ,  Hyoeng-Ki Kim ,  Jung-Hyun Park ,  Ho-Min Son ,  Won-Jun Jang

    IPC: H01L21/3205

    CPC classification number: H01L29/40114

    Abstract: In a method of manufacturing a memory device, a tunnel insulation layer and a floating gate layer are formed on a semiconductor substrate. A top surface of the floating gate layer is converted into a first nitride layer by a first nitridation treatment process. The first nitride layer is converted into a first oxynitride layer by a radical oxidation process. A lower oxide layer is formed on the first oxynitride layer by an LPCVD process. A second nitride layer and an upper oxide layer are formed on the lower oxide layer. A conductive layer is formed on the upper oxide layer. Thus, a multi-layered dielectric layer including the first oxynitride layer, the lower oxide layer, the second nitride layer, the upper oxide layer and the densified second oxynitride layer may have an increased capacitance without having degenerated leakage current characteristics.

    Abstract translation: 在制造存储器件的方法中，在半导体衬底上形成隧道绝缘层和浮栅层。 通过第一氮化处理工艺将浮栅层的顶表面转化为第一氮化物层。 第一氮化物层通过自由基氧化法转化为第一氮氧化物层。 通过LPCVD工艺在第一氮氧化物层上形成低氧化物层。 第二氮化物层和上氧化物层形成在低氧化物层上。 导电层形成在上氧化物层上。 因此，包括第一氧氮化物层，下氧化物层，第二氮化物层，上氧化物层和致密化的第二氧氮化物层的多层电介质层可以具有增加的电容而不具有退化的漏电流特性。

    Buried pattern substrate and manufacturing method thereof
    86.
    发明申请
    Buried pattern substrate and manufacturing method thereof 审中-公开
    埋地图案基板及其制造方法

    公开(公告)号：US20080009128A1

    公开(公告)日：2008-01-10

    申请号：US11708339

    申请日：2007-02-21

    Applicant: Shuhichi Okabe ,  Myung-Sam Kang ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Ji-Eun Kim

    Inventor： Shuhichi Okabe ,  Myung-Sam Kang ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Ji-Eun Kim

    IPC: H01L21/44

    CPC classification number: H05K3/205 ,  H05K3/4038 ,  H05K3/4617 ,  H05K2203/0733 ,  H05K2203/1572

    Abstract: A buried pattern substrate and a manufacturing method thereof are disclosed. A method of manufacturing a buried pattern substrate having a circuit pattern formed on a surface, in which the circuit pattern is connected electrically by a stud bump, includes (a) forming the circuit pattern and the stud bump by depositing a plating layer selectively on a seed layer of a carrier film, where the seed layer is laminated on a surface of the carrier film, (b) laminating and pressing the carrier film on an insulation layer such that the circuit pattern and the stud bump face the insulation layer, and (c) removing the carrier film and the seed layer, allows the circuit interconnection to be realized using a copper (Cu) stud bump, so that a drilling process for interconnection is unnecessary, the degree of freedom for circuit design is improved, a via land is made unnecessary and the size of a via is small, to allow higher density in a circuit.

    Abstract translation: 公开了掩埋图案基板及其制造方法。 一种制造埋设图形衬底的方法，其中电路图案形成在电路图形通过柱形凸块电连接的表面上，包括：（a）通过在 晶种层层叠在载体膜的表面上的载体膜的种子层，（b）在绝缘层上层叠压制载体膜，使得电路图案和柱状凸块面向绝缘层，和 c）去除载体膜和种子层，允许使用铜（Cu）柱状凸块实现电路互连，使得不需要用于互连的钻孔工艺，提高了电路设计的自由度，通孔焊盘 不必要，并且通孔的尺寸小，以允许电路中的较高密度。

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