Abstract:
A compressor is provided in which a rotary member suspended on a stationary member is rotated to compress a refrigerant. The rotary member is suspended on a first stationary member and rotatably supported on a second stationary member spaced apart from the first stationary member, to thereby achieve structural stability, improve operation reliability, and reduce vibration. The components can be easily centered and assembled with an excellent assembly property. In addition, a mounting structure of an elastically-supported vane is improved to ensure lubrication performance and operation reliability. Moreover, a mounting structure of a roller-incorporated vane is improved to reduce vibration and prevent refrigerant leakage, which leads to high compression efficiency.
Abstract:
A compressor is provided in which a rotary member is suspended on a stationary member and rotates to compress a refrigerant. In the stationary member, top and bottom ends of a stationary shaft are fixed to improve structural stability and assembly properties. Bearing covers are provided on a contact portion of the stationary member and the rotary member, such that the rotary member may rotate when suspended on the stationary member, which stabilizes operation. In the rotary member, a vane is integrally formed with a roller and mounted on a vane mounting hole of a cylinder-type rotor. Although, the rotary member is provided on an outer circumferential surface of the stationary member, suction and discharge operations of the refrigerant are performed in an axial direction, which lowers product height. Oil stored in a hermetic container is supplied to a lubrication passage provided between the stationary member and the rotary member.
Abstract:
The present invention relates to a compressor in which a rotary member is suspended on a stationary member and rotated to compress the refrigerant. In the stationary member, top and bottom ends of a stationary shaft are fixed to improve the structural stability and assembly property. Bearing covers are provided on a contact portion of the stationary member and the rotary member such that the rotary member can be rotated when suspended on the stationary member. This stabilizes the operation. In the rotary member, a vane is integrally formed with a roller and mounted on a vane mounting hole of a cylinder-type rotor. This reduces the vibration and prevents refrigerant leakage to improve the compression effect. Although the rotary member is provided on an outer circumferential surface of the stationary member, it is possible to perform the suction and discharge of the refrigerant in the axial direction. This can lower the product height. The oil stored in a hermetic container is supplied to a lubrication passage provided between the stationary member and the rotary member, thereby reducing a friction loss between the components and achieving the operation reliability.
Abstract:
A method and apparatus for making chip assemblies is disclosed that prevent or reduce the cracking and delamination of ultra low-k dielectrics in the back-end-of-line in Si chips that can occur during the chip assembly process. The method and apparatus apply pressure to the top and bottom surfaces of a substrate during the chip bonding process so that the bending and warping of the assembled modules are reduced. The reduced bending and warping prevent or reduce the cracking and delamination of ultra low-k dielectrics.
Abstract:
Example embodiments are directed to a method of forming a semiconductor structure and a semiconductor structure including a semiconductor unit including a protrusion on a front side of the semiconductor unit and a recess on a backside of the semiconductor unit.
Abstract:
A chip stack package is manufactured at a wafer level by forming connection vias in the scribe lanes adjacent the chips and connecting the device chip pads to the connection vias using rerouting lines. A lower chip is then attached and connected to a substrate, which may be a test wafer, and an upper chip is attached and connected to the lower chip, the electrical connections being achieved through their respective connection vias. In addition to the connection vias, the chip stack package may include connection bumps formed between vertically adjacent chips and/or the lower chip and the substrate. The preferred substrate is a test wafer that allows the attached chips to be tested, and replaced if faulty, thereby ensuring that each layer of stacked chips includes only “known-good die” before the next layer of chips is attached thereby increasing the production rate and improving the yield.
Abstract:
The invention relates to a composition of matter comprising a soldering flux, wherein the flux consists essentially of a combination of a fluxing agent and a solvent, and wherein the fluxing agent comprises a keto acid such as levulinic acid or acetylbutyric acid. The flux may also comprises an ester acid, or comprises a mixture of the keto acid with the ester acid. The solvent comprises a mixture of a tacky solvent with a non-tacky solvent. The invention also relates to a process comprising soldering at least two surfaces together, each of which comprises a metal area to which solder can adhere by employing the following steps in any order: applying solder to at least one of the metal areas, aligning the metal areas so that they are superimposed over one another, heating at least one of the areas to a temperature that comprises at least the melting temperature of the solder. The last step comprises joining the superimposed areas to one another. The process employs the flux composition operatively associated with the solder, and in one embodiment the invention comprises a mixture of the flux composition with powdered solder. In another embodiment, the process comprises IMS, C4 and C4NP processes and the solder comprises a lead free solder. The invention also comprises a product produced by the foregoing process or processes.
Abstract:
A chip stack package is manufactured at a wafer level by forming connection vias in the scribe lanes adjacent the chips and connecting the device chip pads to the connection vias using rerouting lines. A lower chip is then attached and connected to a substrate, which may be a test wafer, and an upper chip is attached and connected to the lower chip, the electrical connections being achieved through their respective connection vias. In addition to the connection vias, the chip stack package may include connection bumps formed between vertically adjacent chips and/or the lower chip and the substrate. The preferred substrate is a test wafer that allows the attached chips to be tested, and replaced if faulty, thereby ensuring that each layer of stacked chips includes only “known-good die” before the next layer of chips is attached thereby increasing the production rate and improving the yield.
Abstract:
A wafer level stack structure, including a first wafer including at least one first device chip of a first chip size, wherein each first device chip contains a first plurality of input/output (I/O) pads, a second wafer including at least one second device chip of a second chip size smaller than the first chip size, wherein each second device chip contains a second plurality of I/O pads, wherein the at least one second device chip is increased to the first chip size, wherein the first wafer and the second wafer are stacked, and wherein the first wafer and the second wafer are coupled to each other. A method of forming a wafer level stack structure, including forming a first wafer including at least one first device chip of a first chip size, wherein each first device chip contains a first plurality of input/output (I/O) pads, forming a second wafer including at least one second device chip of a second chip size smaller than the first chip size, wherein each second device chip contains a second plurality of I/O pads, wherein the at least one second device chip is increased to the first chip size, stacking the first wafer and the second wafer, and coupling the first wafer and the second wafer to each other. A system-in-package, including a wafer level stack structure including at least one first device chip with a first plurality of input/output (I/O) pads and at least one second device chip with a second plurality of I/O pads, and a common circuit board to which the wafer level stack structure is connected. A method of forming a system-in-package for containing a wafer level stack structure, including forming a wafer level stack structure including at least one first device chip having a first plurality of input/output (I/O) pads and at least one second device chip having a second plurality of I/O pads, and forming a common circuit board to which the wafer level stack structure is connected.
Abstract:
A method for fabricating a chip-embedded interposer may comprise forming at least one cavity on a silicon substrate, forming a plurality of through vias penetrating the silicon substrate, providing an integrated circuit chip having a plurality of I/O pads, and forming rerouting conductors connected to the I/O pads and the through vias. A stack structure having different kinds of chips may be incorporated at wafer level using the described interposer.