公开(公告)号：US20240125846A1

公开(公告)日：2024-04-18

申请号：US18221824

申请日：2023-07-13

Applicant: SanDisk Technologies LLC

Inventor： Toru Miwa ,  Takashi Murai ,  Hiroyuki Ogawa ,  Nisha Padattil Kuliyampattil

IPC: G01R31/28 ,  G01R1/073 ,  H01L21/66 ,  H01L23/522 ,  H01L25/065

CPC classification number: G01R31/2884 ,  G01R1/07342 ,  H01L22/34 ,  H01L23/5228 ,  H01L25/0657 ,  H01L24/48 ,  H01L2224/48145 ,  H01L2224/48225 ,  H01L2225/06562

Abstract: A semiconductor wafer includes pairs of semiconductor dies having test pads which are electrically coupled to each other to enable testing of pairs of semiconductor dies together at the same time. In this way, even wafers having large numbers of semiconductor dies can be tested with a semiconductor test assembly in a single touch-down test process.

公开(公告)号：US11963352B2

公开(公告)日：2024-04-16

申请号：US17362034

申请日：2021-06-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Peter Rabkin ,  Masaaki Higashitani

IPC: H10B43/27 ,  H01L21/02 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H01L29/24 ,  H10B41/27

CPC classification number: H10B43/27 ,  H01L21/02565 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L29/24 ,  H10B41/27 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1067 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A semiconductor structure includes at least one set of vertical field effect transistors embedded within dielectric material layers overlying a substrate. Each vertical field effect transistor includes a bottom electrode, a metal oxide semiconductor vertical transistor channel, a cylindrical gate dielectric, and a top electrode. A three-dimensional NAND memory array can be provided over the first field effect transistors, and can be electrically connected to the vertical field effect transistors via metal interconnect structures. Alternatively, a three-dimensional NAND memory array can be formed on another substrate, which can be bonded to the substrate via metal-to-metal bonding. The vertical field effect transistors can be employed as switches for bit lines, word lines, or other components of the three-dimensional NAND memory array.

公开(公告)号：US11961572B2

公开(公告)日：2024-04-16

申请号：US17511818

申请日：2021-10-27

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Abhijith Prakash ,  Shubhajit Mukherjee

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26

CPC classification number: G11C16/3459 ,  G11C16/0433 ,  G11C16/08 ,  G11C16/102 ,  G11C16/24 ,  G11C16/26 ,  G11C16/3404

Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines including at least one edge word line and other data word lines. The memory cells are arranged in strings and are configured to retain a threshold voltage corresponding to data states. The strings are organized in rows and a control means is coupled to the word lines and the strings and identifies the at least one edge word line. The control means programs the memory cells of the strings in particular ones of the rows and associated with the at least one edge word line to have an altered distribution of the threshold voltage for one or more of the data states compared to the memory cells of the strings not in particular ones of the rows and not associated with the at least one edge word line during a program operation.

公开(公告)号：US20240121961A1

公开(公告)日：2024-04-11

申请号：US18348727

申请日：2023-07-07

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hiraku HASHIMOTO ,  Eisuke TAKII ,  Shin KOYAMA

IPC: H10B43/27 ,  H01L21/673 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

CPC classification number: H10B43/27 ,  H01L21/67303 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35 ,  C23C16/56

Abstract: A method includes forming a first portion of a layer over a substrate by flowing a reactant gas past the substrate in a first direction, and forming a second portion of the layer on the first portion of the layer by flowing the reactant gas past the substrate in a second direction different from the first direction.

公开(公告)号：US11948902B2

公开(公告)日：2024-04-02

申请号：US17370317

申请日：2021-07-08

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Lin Hou ,  Peter Rabkin ,  Adarsh Rajashekhar ,  Raghuveer S. Makala ,  Masaaki Higashitani

IPC: H01L23/00

CPC classification number: H01L24/08 ,  H01L24/03 ,  H01L2224/0225 ,  H01L2224/02255 ,  H01L2224/0226 ,  H01L2224/03452 ,  H01L2224/03614 ,  H01L2224/08146 ,  H01L2924/1431 ,  H01L2924/1438

Abstract: A bonded assembly includes a first semiconductor die containing a first substrate, first semiconductor devices, and first bonding pads laterally surrounded by a first pad-level dielectric layer. The first pad-level dielectric layer includes at least one first encapsulated airgap located between neighboring pairs of first bonding pads and encapsulated by a first dielectric fill material of the first pad-level dielectric layer. The bonded assembly includes a second semiconductor die containing a second substrate, second semiconductor devices, and second bonding pads laterally surrounded by a second pad-level dielectric layer. Each of the second bonding pads is bonded to a respective one of the first bonding pads.

公开(公告)号：US20240105623A1

公开(公告)日：2024-03-28

申请号：US17934685

申请日：2022-09-23

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ramy Nashed Bassely SAID ,  Jiahui YUAN ,  Lito De La RAMA

IPC: H01L23/535 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11582

CPC classification number: H01L23/535 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11582 ,  H01L2224/08145 ,  H01L2224/80006 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A memory device includes a horizontal source layer which is laterally separated into laterally isolated portions located in adjacent memory blocks by a dielectric backside trench fill structure or a source isolation dielectric structure.

公开(公告)号：US20240105269A1

公开(公告)日：2024-03-28

申请号：US17954489

申请日：2022-09-28

Applicant: SanDisk Technologies LLC

Inventor： Anirudh Amarnath ,  Aravind Suresh ,  Abhijith Prakash

IPC: G11C16/26 ,  G11C16/10 ,  G11C16/24

CPC classification number: G11C16/26 ,  G11C16/102 ,  G11C16/24

Abstract: Systems and methods for bit line modulation to compensate for cell source variation are disclosed. For example, a method for reading data from non-volatile storage comprising determining a first bit line level based on a first programmed data state that is being sensed and determining a second bit line level based on a second programmed data state that is being sensed. As another example, a storage device comprising a first bit line driver configured to generate a first bit line level for a first set of bit lines corresponding to a first set of memory strings based on a first cell source level associated with the first set of memory strings a second bit line driver configured to generate a second bit line level for a second set of bit lines corresponding to a second set of memory strings based on a second cell source level associated with the second set of memory strings.

公开(公告)号：US20240105262A1

公开(公告)日：2024-03-28

申请号：US17952857

申请日：2022-09-26

Applicant: SanDisk Technologies LLC

Inventor： Ramy Nashed Bassely Said ,  Jiahui Yuan ,  Lito De La Rama

IPC: G11C16/04 ,  G06F3/06 ,  G11C16/08 ,  G11C16/14 ,  G11C16/26

CPC classification number: G11C16/0483 ,  G06F3/0619 ,  G06F3/0652 ,  G06F3/0659 ,  G06F3/0679 ,  G11C16/08 ,  G11C16/14 ,  G11C16/26 ,  H01L25/0657

Abstract: To reduce data disturbs and lower current requirements of a 3D NAND memory die, a multi-block plane of non-volatile memory cells has its source line separated into multiple source line regions by introduction of isolation trenches. The plane structure for the NAND memory is maintained, but is broken into multi-block sub-planes, each with an independently biasable source line.

公开(公告)号：US20240096850A1

公开(公告)日：2024-03-21

申请号：US17949069

申请日：2022-09-20

Applicant: SanDisk Technologies LLC

Inventor： Jayavel Pachamuthu ,  Srinivasan Sivaram ,  Masaaki Higashitani

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L25/18

CPC classification number: H01L25/0657 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/48 ,  H01L25/18 ,  H01L25/50 ,  H01L24/16 ,  H01L2224/05026 ,  H01L2224/05083 ,  H01L2224/05166 ,  H01L2224/05186 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/08145 ,  H01L2224/16227 ,  H01L2224/48105 ,  H01L2224/48145 ,  H01L2225/06506 ,  H01L2924/04941

Abstract: An integrated controller, logic circuit and memory array (“CLM”) semiconductor device includes stacked controller, memory array logic circuit and memory array wafers, or individual dies diced therefrom, which together operate as a single, integrated semiconductor flash memory device. The memory array logic circuit dies and/or the memory array dies may be formed with full-thickness plated or filled vias connecting to bond pads on opposed surfaces of the dies. The bond pads of the respective stacked semiconductor dies may be aligned and affixed to each other to electrically and mechanically couple each of the semiconductor dies in the respective wafers together.

公开(公告)号：US11935622B2

公开(公告)日：2024-03-19

申请号：US17725441

申请日：2022-04-20

Applicant: SanDisk Technologies LLC

Inventor： Sajal Mittal ,  Sneha Bhatia

IPC: G11C7/10 ,  G11C7/22

CPC classification number: G11C7/222 ,  G11C7/1012 ,  G11C7/1039 ,  G11C7/1057 ,  G11C7/1084

Abstract: A data path architecture and corresponding method of operation are disclosed that permit a first-in-first out (FIFO) buffer to immediately flush data—including potentially invalid initial byte(s)—upon receipt of a high-speed clock signal, and according to which, a delay difference between a data path clock signal and a high-speed clock signal is compensated for at a controller side by, for example, adjusting RE latency to discard/ignore the initially invalid bytes rather than by modifying FIFO depth or varying a number of delay stages in the high-speed clock signal path in order to satisfy the FIFO depth. Because FIFO depth is not used to absorb the clock signal delay difference, there is no need to modify the architecture (e.g., change the depth of a FIFO) to accommodate variation in the clock signal delay difference across different products/product generations, thereby providing high scalability.