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    Power Driven Optimization For Flash Memory
    84.
    发明申请
    Power Driven Optimization For Flash Memory 审中-公开

    公开(公告)号：US20170110194A1

    公开(公告)日：2017-04-20

    申请号：US15244947

    申请日：2016-08-23

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Vipin Tiwari ,  Nhan Do

    IPC: G11C16/12 ,  G11C16/26 ,  G11C16/30 ,  G11C16/14

    CPC classification number: G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  G11C16/30 ,  H01L27/11582 ,  H01L28/00

    Abstract: A memory device, and method of operation, includes an array of non-volatile memory cells and a controller. The controller is configured to perform an operation (e.g. erase, program, etc.) on a first plurality of the non-volatile memory cells using operational voltages with a first energy margin, and perform the same operation on a second plurality of the non-volatile memory cells using operational voltages with a second energy margin that is greater than the first energy margin. The operations of varying energy margins are based on the required storage longevity of the data being stored (lower energy margins for data being stored for shorter periods of time) to save energy and wear.

    Non-volatile Split Gate Memory Cells With Integrated High K Metal Gate Logic Device And Metal-Free Erase Gate, And Method Of Making Same
    85.
    发明申请
    Non-volatile Split Gate Memory Cells With Integrated High K Metal Gate Logic Device And Metal-Free Erase Gate, And Method Of Making Same 有权
    具有集成高K金属栅极逻辑器件和无金属擦除栅极的非易失性分离栅极存储单元及其制造方法

    公开(公告)号：US20170025427A1

    公开(公告)日：2017-01-26

    申请号：US15180376

    申请日：2016-06-13

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Chien-Sheng Su ,  Jeng-Wei Yang ,  Feng Zhou

    IPC: H01L27/115 ,  H01L29/66 ,  H01L29/423

    CPC classification number: H01L27/11531 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42328 ,  H01L29/66484 ,  H01L29/66825 ,  H01L29/7881

    Abstract: A method of forming split gate non-volatile memory cells on the same chip as logic and high voltage devices having HKMG logic gates. The method includes forming the source and drain regions, floating gates, control gates, and the poly layer for the erase gates and word line gates in the memory area of the chip. A protective insulation layer is formed over the memory area, and an HKMG layer and poly layer are formed on the chip, removed from the memory area, and patterned in the logic areas of the chip to form the logic gates having varying amounts of underlying insulation.

    Abstract translation: 在具有HKMG逻辑门的逻辑和高电压器件的同一芯片上形成分离栅非易失性存储单元的方法。 该方法包括在芯片的存储器区域中形成用于擦除栅极和字线栅极的源极和漏极区域，浮动栅极，控制栅极和多晶硅层。 在存储区域上形成保护绝缘层，并且在芯片上形成HKMG层和多晶硅层，从存储区域移除，并在芯片的逻辑区域中图案化以形成具有不同量的底层绝缘体的逻辑门 。

    Self-Aligned Source For Split-Gate Non-volatile Memory Cell
    86.
    发明申请
    Self-Aligned Source For Split-Gate Non-volatile Memory Cell 有权
    分离门非易失性存储单元的自对准源

    公开(公告)号：US20170025424A1

    公开(公告)日：2017-01-26

    申请号：US15287672

    申请日：2016-10-06

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Chien-Sheng Su ,  Jeng-Wei Yang ,  Yueh-Hsin Chen

    IPC: H01L27/115 ,  H01L29/66 ,  H01L29/16 ,  H01L29/423

    CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L21/823425 ,  H01L29/1608 ,  H01L29/42328 ,  H01L29/66825

    Abstract: A memory device having a pair of conductive floating gates with inner sidewalls facing each other, and disposed over and insulated from a substrate of first conductivity type. A pair of spaced apart conductive control gates each disposed over and insulated from one of the floating gates, and each including inner sidewalls facing each other. A pair of first spacers of insulation material extending along control gate inner sidewalls and over the floating gates. The floating gate inner sidewalls are aligned with side surfaces of the first spacers. A pair of second spacers of insulation material each extend along one of the first spacers and along one of the floating gate inner sidewalls. A trench formed into the substrate having sidewalls aligned with side surfaces of the second spacers. Silicon carbon disposed in the trench. Material implanted into the silicon carbon forming a first region having a second conductivity type.

    Abstract translation: 一种具有一对导电浮动栅极的存储器件，所述导电浮动栅极具有彼此相对的内侧壁，并且设置在第一导电类型的衬底上并与其绝缘。 一对间隔开的导电控制栅极，每个导电控制栅极设置在浮动栅极中的一个上并与其绝缘，并且每个包括面向彼此的内侧壁。 一对绝缘材料的第一间隔物，沿着控制栅极内侧壁和浮动栅极延伸。 浮动门内侧壁与第一间隔件的侧表面对准。 绝缘材料的一对第二间隔物各自沿着第一间隔件中的一个并且沿着浮动栅极内侧壁中的一个延伸。 形成在衬底中的沟槽，其具有与第二间隔物的侧表面对齐的侧壁。 设置在沟槽中的硅碳。 材料注入到硅碳中，形成具有第二导电类型的第一区域。

    Non-volatile memory cell having a trapping charge layer in a trench and an array and a method of manufacturing therefor
    87.
    发明授权
    Non-volatile memory cell having a trapping charge layer in a trench and an array and a method of manufacturing therefor 有权
    在沟槽中具有捕获电荷层的阵列的非易失性存储单元及其制造方法

    公开(公告)号：US09548380B2

    公开(公告)日：2017-01-17

    申请号：US13829111

    申请日：2013-03-14

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Nhan Do

    IPC: G11C11/34 ,  H01L29/792 ,  H01L21/3205 ,  H01L29/788 ,  H01L29/66 ,  H01L27/105 ,  H01L29/423 ,  H01L27/115

    CPC classification number: H01L29/66833 ,  H01L21/0217 ,  H01L27/1052 ,  H01L27/11565 ,  H01L27/11568 ,  H01L29/42344 ,  H01L29/42352 ,  H01L29/66825 ,  H01L29/7926

    Abstract: A memory cell formed by forming a trench in the surface of a substrate. First and second spaced apart regions are formed in the substrate with a channel region therebetween. The first region is formed under the trench. The channel region includes a first portion that extends along a sidewall of the trench and a second portion that extends along the surface of the substrate. A charge trapping layer in the trench is adjacent to and insulated from the first portion of the channel region for controlling the conduction of the channel region first portion. An electrically conductive gate in the trench is adjacent to and insulated from the charge trapping layer and from the first region and is capacitively coupled to the charge trapping layer. An electrically conductive control gate is disposed over and insulated from the second portion of the channel region for controlling its conduction.

    Abstract translation: 通过在衬底表面形成沟槽形成的存储单元。 第一和第二间隔开的区域形成在衬底中，其间具有通道区域。 第一区域形成在沟槽下方。 沟道区域包括沿着沟槽的侧壁延伸的第一部分和沿衬底的表面延伸的第二部分。 沟槽中的电荷捕获层与沟道区的第一部分相邻并与其绝缘，用于控制沟道区第一部分的导通。 沟槽中的导电栅极与电荷俘获层相邻并且与第一区绝缘，并与电荷捕获层电容耦合。 导电控制栅极设置在沟道区域的第二部分上并与沟道区域的第二部分绝缘，用于控制其导通。

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