利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

741 条记录 (耗时 0.042 秒)

    METHOD FOR REDUCING POWER CONSUMPTION IN ELECTRONIC APPARATUS
    81.
    发明申请
    METHOD FOR REDUCING POWER CONSUMPTION IN ELECTRONIC APPARATUS 有权
    降低电子设备功耗的方法

    公开(公告)号：US20150067367A1

    公开(公告)日：2015-03-05

    申请号：US14057277

    申请日：2013-10-18

    申请人： VIA TECHNOLOGIES, INC.

    发明人： Cheng-Ming HUANG

    IPC分类号： G06F1/32

    CPC分类号： G06F1/324 ,  G06F1/3212 ,  Y02D10/126 ,  Y02D10/174

    摘要： An electronic apparatus is provided. The electronic apparatus includes a serial advanced technology attachment (SATA) physical layer, a clock generator and a control unit. The SATA physical layer is configured to provide connection with an SATA device and perform data transmission with the SATA device is performed at a first clock frequency. The clock generator is configured to provide a clock signal having the first clock frequency to the SATA physical layer. When at least one specific event is detected by the control unit, the control unit controls the clock generator to provide the clock signal having a second clock frequency to the SATA physical layer, so that the SATA physical layer performs data transmission with the SATA device at the second clock frequency. The second clock frequency is lower than the first clock frequency.

    摘要翻译： 提供电子设备。 电子设备包括串行高级技术附件（SATA）物理层，时钟发生器和控制单元。 SATA物理层配置为提供与SATA设备的连接并执行数据传输，SATA设备以第一时钟频率执行。 时钟发生器被配置为向SATA物理层提供具有第一时钟频率的时钟信号。 当由控制单元检测到至少一个特定事件时，控制单元控制时钟发生器以向SATA物理层提供具有第二时钟频率的时钟信号，使得SATA物理层与SATA设备进行数据传输 第二个时钟频率。 第二个时钟频率低于第一个时钟频率。

    MICROPROCESSOR WITH BOOT INDICATOR THAT INDICATES A BOOT ISA OF THE MICROPROCESSOR AS EITHER THE X86 ISA OR THE ARM ISA
    84.
    发明申请
    MICROPROCESSOR WITH BOOT INDICATOR THAT INDICATES A BOOT ISA OF THE MICROPROCESSOR AS EITHER THE X86 ISA OR THE ARM ISA 有权
    具有引导指示器的微处理器显示了作为X86 ISA或ARM ISA的微处理器的引导ISA

    公开(公告)号：US20150067301A1

    公开(公告)日：2015-03-05

    申请号：US14526029

    申请日：2014-10-28

    申请人： VIA TECHNOLOGIES, INC.

    发明人： G. GLENN HENRY ,  TERRY PARKS ,  RODNEY E. HOOKER

    IPC分类号： G06F15/82 ,  G06F9/38 ,  G06F9/30

    CPC分类号： G06F9/441 ,  G06F9/265 ,  G06F9/30043 ,  G06F9/30072 ,  G06F9/30076 ,  G06F9/30105 ,  G06F9/30123 ,  G06F9/30145 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/30189 ,  G06F9/30196 ,  G06F9/3802 ,  G06F9/4401 ,  G06F9/4403 ,  G06F15/82

    摘要： A microprocessor includes a plurality of registers that holds an architectural state of the microprocessor and an indicator that indicates a boot instruction set architecture (ISA) of the microprocessor as either the x86 ISA or the Advanced RISC Machines (ARM) ISA. The microprocessor also includes a hardware instruction translator that translates x86 ISA instructions and ARM ISA instructions into microinstructions. The hardware instruction translator translates, as instructions of the boot ISA, the initial ISA instructions that the microprocessor fetches from architectural memory space after receiving a reset signal. The microprocessor also includes an execution pipeline, coupled to the hardware instruction translator. The execution pipeline executes the microinstructions to generate results defined by the x86 ISA and ARM ISA instructions. In response to the reset signal, the microprocessor initializes its architectural state in the plurality of registers as defined by the boot ISA prior to fetching the initial ISA instructions.

    摘要翻译： 微处理器包括保持微处理器架构状态的多个寄存器和指示微处理器的引导指令集体系结构（ISA）作为x86 ISA或高级RISC机器（ARM）ISA的指示符。 微处理器还包括硬件指令转换器，将x86 ISA指令和ARM ISA指令转换为微指令。 作为引导ISA的指令，硬件指令转换器将转换为接收复位信号后微处理器从架构存储器空间中提取的初始ISA指令。 微处理器还包括耦合到硬件指令转换器的执行流水线。 执行流水线执行微指令以生成由x86 ISA和ARM ISA指令定义的结果。 响应于复位信号，微处理器在获取初始ISA指令之前初始化由引导ISA定义的多个寄存器中的架构状态。

    CORRECTABLE CONFIGURATION DATA COMPRESSION AND DECOMPRESSION SYSTEM
    87.
    发明申请
    CORRECTABLE CONFIGURATION DATA COMPRESSION AND DECOMPRESSION SYSTEM 有权
    正确的配置数据压缩和解密系统

    公开(公告)号：US20150058695A1

    公开(公告)日：2015-02-26

    申请号：US13972812

    申请日：2013-08-21

    申请人： VIA TECHNOLOGIES, INC.

    发明人： G. Glenn Henry ,  Dinesh K. Jain

    IPC分类号： H03M13/05 ,  G06F11/10

    CPC分类号： G06F11/10 ,  H03M7/702 ,  H03M13/05

    摘要： An apparatus has a shared fuse array and a plurality of microprocessor cores. The shared fuse array is disposed on a die, the shared fuse array having a plurality of semiconductor fuses programmed with compressed configuration data and error checking and correction (ECC) codes. The plurality of microprocessor cores is disposed on the die, where each of the plurality of microprocessor cores is coupled to the shared fuse array and is configured to access all of the compressed configuration data during power-up/reset, for initialization of elements within the each of the plurality of cores. The each of the plurality of cores includes a reset controller that is configured to access the compressed configuration data and the ECC codes, to correct errors resulting in corrected compressed configuration data, to decompress all of the corrected compressed configuration data, and to distribute decompressed configuration data to initialize the elements.

    摘要翻译： 一种装置具有共享熔丝阵列和多个微处理器核心。 共享保险丝阵列设置在管芯上，共享保险丝阵列具有多个半导体保险丝，其编程有压缩配置数据和错误校验（ECC）代码。 多个微处理器核心设置在管芯上，其中多个微处理器核心中的每一个耦合到共享熔丝阵列，并且被配置为在上电/复位期间访问所有压缩的配置数据，用于初始化 多个核心中的每一个。 所述多个核心中的每一个包括复位控制器，其被配置为访问所述压缩配置数据和所述ECC代码，以校正导致校正的压缩配置数据的错误，以解压缩所有经校正的压缩配置数据，并且分发解压缩配置 数据初始化元素。

    APPARATUS AND METHOD FOR EXTENDED CACHE CORRECTION
    88.
    发明申请
    APPARATUS AND METHOD FOR EXTENDED CACHE CORRECTION 审中-公开
    扩展高速缓存校正的设备和方法

    公开(公告)号：US20150058564A1

    公开(公告)日：2015-02-26

    申请号：US13972481

    申请日：2013-08-21

    申请人： VIA TECHNOLOGIES, INC.

    发明人： G. Glenn Henry ,  Dinesh K. Jain

    IPC分类号： G06F12/08 ,  G06F3/06

    CPC分类号： G06F12/0802 ,  G06F3/0619 ,  G06F3/0632 ,  G06F3/0673 ,  G06F11/1008 ,  G06F15/76 ,  G11C29/787 ,  G11C29/802

    摘要： An apparatus includes a semiconductor fuse array, a cache memory, and a plurality of cores. The semiconductor fuse array is disposed on a die, into which is programmed the configuration data. The semiconductor fuse array has a first plurality of semiconductor fuses that is configured to store compressed cache correction data. The a cache memory is disposed on the die. The plurality of cores is disposed on the die, where each of the plurality of cores is coupled to the semiconductor fuse array and the cache memory, and is configured to access the semiconductor fuse array upon power-up/reset, to decompress the compressed cache correction data, and to distribute decompressed cached correction data to initialize the cache memory.

    摘要翻译： 一种装置包括半导体熔丝阵列，高速缓冲存储器和多个核。 半导体熔丝阵列设置在芯片上，其中编程了配置数据。 半导体熔丝阵列具有第一多个半导体熔丝，其被配置为存储压缩的高速缓存校正数据。 高速缓冲存储器设置在管芯上。 多个芯设置在管芯上，其中多个芯中的每个芯耦合到半导体熔丝阵列和高速缓冲存储器，并且被配置为在上电/复位时访问半导体熔丝阵列，以解压缩压缩高速缓存 校正数据，并且分发解压缩的缓存校正数据以初始化高速缓冲存储器。

    Frequency-control circuits and signal generation devices using the same
    90.
    发明授权
    Frequency-control circuits and signal generation devices using the same 有权
    频率控制电路和使用其的信号发生装置

    公开(公告)号：US08952734B2

    公开(公告)日：2015-02-10

    申请号：US13850666

    申请日：2013-03-26

    申请人： Via Technologies, Inc.

    发明人： Yeong-Sheng Lee

    IPC分类号： H03L7/00 ,  H03L7/14 ,  H04L27/00

    CPC分类号： H03L7/14 ,  H03L7/0816 ,  H03L7/0891 ,  H03L7/099 ,  H04L27/00

    摘要： A signal generation device is provided to generate an output signal with constant frequency. The signal generation device includes a frequency-control circuit and a voltage-controlled delay line. The frequency-control circuit includes a pulse generator, generating a reference pulse signal according to a transition of the reference signal and a comparison pulse signal according to a transition of the comparison result signal, to re-shape the reference signal and the comparison result signal into narrow pulses suitable for clocking and resetting flip-flops.

    摘要翻译： 提供信号发生装置以产生具有恒定频率的输出信号。 信号发生装置包括频率控制电路和电压控制延迟线。 频率控制电路包括脉冲发生器，根据比较结果信号的转变，根据参考信号的转变和比较脉冲信号产生参考脉冲信号，以重新形成参考信号和比较结果信号 转换成适合时钟和复位触发器的窄脉冲。