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    Apparatuses and methods for transposing select gates
    81.
    发明授权
    Apparatuses and methods for transposing select gates 有权
    用于转置选择门的装置和方法

    公开(公告)号：US09064576B2

    公开(公告)日：2015-06-23

    申请号：US14332982

    申请日：2014-07-16

    Applicant: Micron Technology, Inc.

    Inventor： Toru Tanzawa

    IPC: H01L21/70 ,  G11C16/04 ,  H01L27/02 ,  H01L27/115 ,  G11C16/08

    CPC classification number: G11C16/0483 ,  G11C16/08 ,  H01L27/0207 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556

    Abstract: Apparatuses and methods for transposing select gates, such as in a computing system and/or memory device, are provided. One example apparatus can include a group of memory cells and select gates electrically coupled to the group of memory cells. The select gates are arranged such that a pair of select gates are adjacent to each other along a first portion of each of the pair of select gates and are non-adjacent along a second portion of each of the pair of select gates.

    Abstract translation: 提供了用于转置选择门的装置和方法，诸如在计算系统和/或存储装置中。 一个示例性设备可以包括一组存储器单元和电耦合到该组存储器单元的选择栅极。 选择栅极被布置成使得一对选择栅极沿着该对选择栅极中的每一个的第一部分彼此相邻并且沿着该对选择栅极中的每一个的第二部分不相邻。

    RANDOM TELEGRAPH SIGNAL NOISE REDUCTION SCHEME FOR SEMICONDUCTOR MEMORIES
    84.
    发明申请
    RANDOM TELEGRAPH SIGNAL NOISE REDUCTION SCHEME FOR SEMICONDUCTOR MEMORIES 有权
    半导体存储器的随机电视信号减噪方案

    公开(公告)号：US20140321216A1

    公开(公告)日：2014-10-30

    申请号：US14331056

    申请日：2014-07-14

    Applicant: Micron Technology, Inc.

    Inventor： Toru Tanzawa

    IPC: G11C16/04 ,  G11C16/26

    CPC classification number: G11C16/26 ,  G11C7/00 ,  G11C16/0408 ,  G11C16/10 ,  G11C16/12 ,  G11C16/3459

    Abstract: Embodiments are provided that include a method including providing a first pulsed gate signal to a selected memory cell, wherein the pulsed gate signal alternates between a first voltage level and a second voltage level during a time period and sensing a data line response to determine data stored on the selected memory of cells. Further embodiments provide a system including a memory device, having a regulator circuit coupled to a plurality of access lines of a NAND memory cell, and a switching circuit configured to sequentially bias at least one of the plurality of the access lines between a first voltage level and a second voltage level based on an input signal.

    Abstract translation: 提供的实施例包括一种方法，包括向所选择的存储单元提供第一脉冲栅极信号，其中脉冲栅极信号在一段时间段内在第一电压电平和第二电压电平之间交替并感测数据线响应以确定存储的数据 在选定的单元格内存上。 另外的实施例提供一种包括存储器件的系统，该存储器件具有耦合到NAND存储器单元的多个访问线路的调节器电路，以及切换电路，被配置为顺序地将多个接入线路中的至少一个在第一电压电平 以及基于输入信号的第二电压电平。

    INTERCONNECTIONS FOR 3D MEMORY
    85.
    发明申请
    INTERCONNECTIONS FOR 3D MEMORY 有权
    三维存储器的互连

    公开(公告)号：US20140241026A1

    公开(公告)日：2014-08-28

    申请号：US13774522

    申请日：2013-02-22

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Toru Tanzawa

    IPC: G11C5/06

    CPC classification number: G11C5/063 ,  G11C5/02 ,  G11C5/06 ,  G11C7/12 ,  G11C7/222 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11551

    Abstract: Apparatuses and methods for interconnections for 3D memory are provided. One example apparatus can include a stack of materials including a plurality of pairs of materials, each pair of materials including a conductive line formed over an insulation material. The stack of materials has a stair step structure formed at one edge extending in a first direction. Each stair step includes one of the pairs of materials. A first interconnection is coupled to the conductive line of a stair step, the first interconnection extending in a second direction substantially perpendicular to a first surface of the stair step.

    Abstract translation: 提供了用于3D存储器的互连的装置和方法。 一个示例性设备可以包括包括多对材料的材料堆叠，每对材料包括在绝缘材料上形成的导电线。 一叠材料具有在沿第一方向延伸的一个边缘处形成的阶梯结构。 每个阶梯步骤包括一对材料之一。 第一互连件耦合到阶梯级的导线，第一互连件在基本上垂直于楼梯台阶的第一表面的第二方向上延伸。

    APPARATUSES AND METHODS INCLUDING MEMORY WRITE OPERATION
    86.
    发明申请
    APPARATUSES AND METHODS INCLUDING MEMORY WRITE OPERATION 有权
    包括存储器写操作的设备和方法

    公开(公告)号：US20140204677A1

    公开(公告)日：2014-07-24

    申请号：US14222062

    申请日：2014-03-21

    Applicant: Micron Technology, Inc.

    Inventor： Toru Tanzawa

    IPC: G11C16/04

    CPC classification number: G11C16/04 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/12 ,  G11C16/3418

    Abstract: Some embodiments include apparatuses and methods having memory cells and access lines coupled to the memory cells. In one such apparatus, the access lines include a first access line and a second access line. The first access line can be adjacent to the second access line. The memory cells include a memory cell associated with the second access line. A module can be configured to apply a voltage to the first access line during an operation of accessing the memory cell associated with the second access line, and to place the second access line in a floating state during at least a portion of a time interval within the operation. Other embodiments including additional apparatus and methods are described.

    Abstract translation: 一些实施例包括具有耦合到存储器单元的存储器单元和存取线的装置和方法。 在一种这样的装置中，接入线路包括第一接入线路和第二接入线路。 第一条接入线可以与第二条接入线相邻。 存储器单元包括与第二访问线相关联的存储单元。 模块可以被配置为在访问与第二接入线路相关联的存储器单元的操作期间将电压施加到第一接入线路，并且在第二接入线路的时间间隔的至少一部分期间将第二接入线路置于浮置状态 的操作。 描述包括附加装置和方法的其它实施例。

    APPARATUSES AND METHODS INVOLVING ACCESSING MEMORY CELLS
    87.
    发明申请
    APPARATUSES AND METHODS INVOLVING ACCESSING MEMORY CELLS 有权
    涉及存取细胞的装置和方法

    公开(公告)号：US20140169098A1

    公开(公告)日：2014-06-19

    申请号：US13718801

    申请日：2012-12-18

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Toru Tanzawa ,  Satoru Tamada ,  Koichi Kawai ,  Tetsuji Manabe

    IPC: G11C7/00 ,  G11C16/06

    CPC classification number: G11C8/12 ,  G11C7/00 ,  G11C7/18 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/08 ,  G11C2207/005 ,  G11C2207/2245

    Abstract: Apparatuses and methods involving accessing memory cells are described. In one such method, chunks of memory cells in a memory array are enabled to be accessed and then one or more of the chunks are disabled from being accessed. In one such apparatus, an array includes chunks of memory cells and a chunk selector circuit coupled to each chunk to enable the memory cells in the respective chunk to be accessed. Additional embodiments are described.

    Abstract translation: 描述了涉及访问存储器单元的装置和方法。 在一种这样的方法中，可以访问存储器阵列中的存储器单元块，然后禁止一个或多个块被访问。 在一种这样的装置中，阵列包括存储器单元的块和耦合到每个块的块选择器电路，以使得可以访问相应块中的存储器单元。 描述其他实施例。

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