公开(公告)号：US08970033B2

公开(公告)日：2015-03-03

申请号：US13035586

申请日：2011-02-25

申请人： Yu-Feng Chen ,  Yuh Chern Shieh ,  Tsung-Shu Lin ,  Han-Ping Pu ,  Jiun Yi Wu ,  Tin-Hao Kuo

发明人： Yu-Feng Chen ,  Yuh Chern Shieh ,  Tsung-Shu Lin ,  Han-Ping Pu ,  Jiun Yi Wu ,  Tin-Hao Kuo

IPC分类号： H01L23/498 ,  H01L23/00

CPC分类号： H01L24/16 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/17 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16013 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00013 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599

摘要： A device includes a work piece, and a metal trace on a surface of the work piece. A Bump-on-Trace (BOT) is formed at the surface of the work piece. The BOT structure includes a metal bump, and a solder bump bonding the metal bump to a portion of the metal trace. The metal trace includes a metal trace extension not covered by the solder bump.

摘要翻译： 一种装置包括工件和工件表面上的金属迹线。 在工件的表面形成凸起跟踪（BOT）。 BOT结构包括金属凸块和将金属凸块接合到金属迹线的一部分的焊料凸块。 金属迹线包括未被焊料凸块覆盖的金属迹线延伸。

公开(公告)号：US08927333B2

公开(公告)日：2015-01-06

申请号：US13302059

申请日：2011-11-22

申请人： Tsung-Shu Lin ,  Yu-Ling Tsai ,  Han-Ping Pu

发明人： Tsung-Shu Lin ,  Yu-Ling Tsai ,  Han-Ping Pu

IPC分类号： H01L21/00 ,  H01L21/76 ,  H01L23/48 ,  H01L23/552 ,  H01L25/10

CPC分类号： H01L25/105 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/1017 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00012

摘要： A package-on-package arrangement for maintaining die alignment during a reflow operation is provided. A first top die has a first arrangement of solder bumps. A bottom package has a first electrical arrangement to electrically connect to the first arrangement of solder bumps. A die carrier has a plurality of mounting regions defined on its bottom surface, wherein the first top die is adhered to the die carrier at a first of the plurality of mounting regions. One of a second top die and a dummy die having a second arrangement of solder bumps is also fixed to the die carrier at a second of the plurality of mounting regions of the die carrier. The first and second arrangements of solder bumps are symmetric to one another, therein balancing a surface tension during a reflow operation, and generally fixing an orientation of the die carrier with respect to the bottom package.

摘要翻译： 提供了一种用于在回流操作期间维持管芯对准的封装封装布置。 第一顶模具有焊料凸块的第一布置。 底部封装具有电连接到第一焊料凸点布置的第一电气布置。 模具载体具有限定在其底表面上的多个安装区域，其中第一顶模在多个安装区域中的第一个处粘附到模具载体。 具有第二排列焊料凸点的第二顶模和虚模具之一也在模具载体的多个安装区域的第二位置处固定到模具载体。 焊料凸块的第一和第二布置彼此对称，其中在回流操作期间平衡表面张力，并且通常相对于底部封装固定模具载体的取向。

公开(公告)号：US08759964B2

公开(公告)日：2014-06-24

申请号：US11779192

申请日：2007-07-17

申请人： Han-Ping Pu ,  Mirng-Ji Lii

发明人： Han-Ping Pu ,  Mirng-Ji Lii

IPC分类号： H01L21/00

CPC分类号： H01L21/568 ,  H01L21/561 ,  H01L21/6835 ,  H01L23/3107 ,  H01L24/13 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/20 ,  H01L2224/97 ,  H01L2924/00013 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/82 ,  H01L2224/29099 ,  H01L2924/00

摘要： A method of forming a package structure with reduced damage to semiconductor dies is provided. The method includes providing a die comprising bond pads on a top surface of the die; forming bumps on the bond pads of the die, wherein the bumps have top surfaces higher than the top surface of the die; mounting the die on a chip carrier, wherein the bumps are attached to the chip carrier; molding the die onto the chip carrier with a molding compound; de-mounting the chip carrier from the die; and forming redistribution traces over, and electrically connected to, the bumps of the die.

摘要翻译： 提供一种形成具有对半导体管芯的损伤减小的封装结构的方法。 所述方法包括提供在所述管芯的顶表面上包括接合焊盘的管芯; 在所述模具的接合焊盘上形成凸起，其中所述凸起具有高于所述模具的顶表面的顶表面; 将所述管芯安装在芯片载体上，其中所述凸块附接到所述芯片载体上; 用模塑料将模具成型到芯片载体上; 将芯片载体从芯片上拆下; 以及在模具的凸起上形成并电连接到模具的凸块上的再分布迹线。

公开(公告)号：US20130119532A1

公开(公告)日：2013-05-16

申请号：US13294859

申请日：2011-11-11

申请人： Chun-Hung Lin ,  Yu-Feng Chen ,  Tsung-Shu Lin ,  Han-Ping Pu ,  Hsien-Wei Chen

发明人： Chun-Hung Lin ,  Yu-Feng Chen ,  Tsung-Shu Lin ,  Han-Ping Pu ,  Hsien-Wei Chen

IPC分类号： H01L23/485

CPC分类号： H01L24/14 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/525 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/0233 ,  H01L2224/02331 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05024 ,  H01L2224/0508 ,  H01L2224/05085 ,  H01L2224/05558 ,  H01L2224/05569 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/06131 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2224/1403 ,  H01L2224/14131 ,  H01L2224/14135 ,  H01L2224/14136 ,  H01L2224/14179 ,  H01L2224/16225 ,  H01L2224/17051 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/351 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2224/05552

摘要： A chip scale semiconductor device comprises a semiconductor die, a first bump and a second bump. The first bump having a first diameter and a first height is formed on an outer region of the semiconductor die. A second bump having a second diameter and a second height is formed on an inner region of the semiconductor die. The second diameter is greater than the first diameter while the second height is the same as the first height. By changing the shape of the bump, the stress and strain can be redistributed through the bump. As a result, the thermal cycling reliability of the chip scale semiconductor device is improved.

摘要翻译： 芯片级半导体器件包括半导体管芯，第一突起和第二突起。 具有第一直径和第一高度的第一凸块形成在半导体管芯的外部区域上。 具有第二直径和第二高度的第二凸起形成在半导体管芯的内部区域上。 第二直径大于第一直径，而第二高度与第一高度相同。 通过改变凸块的形状，应力和应变可通过凸块重新分布。 结果，提高了芯片级半导体器件的热循环可靠性。

公开(公告)号：US08373282B2

公开(公告)日：2013-02-12

申请号：US13162394

申请日：2011-06-16

申请人： Yu-Feng Chen ,  Yu-Ling Tsai ,  Han-Ping Pu ,  Hung-Jui Kuo ,  Yu Yi Huang

发明人： Yu-Feng Chen ,  Yu-Ling Tsai ,  Han-Ping Pu ,  Hung-Jui Kuo ,  Yu Yi Huang

IPC分类号： H01L23/52 ,  H01L23/48 ,  H01L29/40

CPC分类号： H01L23/562 ,  H01L23/293 ,  H01L23/3114 ,  H01L23/3192 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/131 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2224/05552

摘要： A structure includes a metal pad over a semiconductor substrate, a passivation layer having a portion over the metal pad, and a first polyimide layer over the passivation layer, wherein the first polyimide layer has a first thickness and a first Young's modulus. A post-passivation interconnect (PPI) includes a first portion over the first polyimide layer, and a second portion extending into the passivation layer and the first polyimide layer. The PPI is electrically coupled to the metal pad. A second polyimide layer is over the PPI. The second polyimide layer has a second thickness and a second Young's modulus. At least one of a thickness ratio and a Young's modulus ratio is greater than 1.0, wherein the thickness ratio is the ratio of the first thickness to the second thickness, and the Young's modulus ratio is the ratio of the second Young's modulus to the first Young's modulus.

摘要翻译： 一种结构包括半导体衬底上的金属焊盘，具有金属焊盘上方的一部分的钝化层以及钝化层上的第一聚酰亚胺层，其中第一聚酰亚胺层具有第一厚度和第一杨氏模量。 后钝化互连（PPI）包括在第一聚酰亚胺层之上的第一部分，以及延伸到钝化层和第一聚酰亚胺层中的第二部分。 PPI电耦合到金属垫。 第二个聚酰亚胺层位于PPI之上。 第二聚酰亚胺层具有第二厚度和第二杨氏模量。 厚度比和杨氏模量比中的至少一个大于1.0，其中厚度比是第一厚度与第二厚度的比率，杨氏模量比是第二杨氏模量与第一杨氏模量之比 模数。

公开(公告)号：US07888236B2

公开(公告)日：2011-02-15

申请号：US11798432

申请日：2007-05-14

申请人： Han-Ping Pu ,  Bai-Yao Lou ,  Dean Wang ,  Ching-Wen Hsiao ,  Kai-Ming Ching ,  Chen-Cheng Kuo ,  Wen-Chih Chiou ,  Ding-Chung Lu ,  Shang-Yun Hou

发明人： Han-Ping Pu ,  Bai-Yao Lou ,  Dean Wang ,  Ching-Wen Hsiao ,  Kai-Ming Ching ,  Chen-Cheng Kuo ,  Wen-Chih Chiou ,  Ding-Chung Lu ,  Shang-Yun Hou

IPC分类号： H01L21/00

CPC分类号： H01L21/78 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/051 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/11 ,  H01L2924/00014

摘要： A method for packaging a semiconductor device disclosed. A substrate comprising a plurality of dies, separated by scribe line areas respectively is provided, wherein at least one layer is overlying the substrate. A portion of the layer within the scribe lines area is removed by photolithography and etching to form openings. The substrate is sawed along the scribe line areas, passing the openings. In alternative embodiment, a first substrate comprising a plurality of first dies separated by first scribe line areas respectively is provided, wherein at least one first structural layer is overlying the first substrate. The first structural layer is patterned to form first openings within the first scribe line areas. A second substrate comprising a plurality of second dies separated by second scribe line areas respectively is provided, wherein at least one second structural layer is overlying the substrate. The second structural layer is patterned to form second openings within the second scribe line areas. The first substrate and the second substrate are bonded to form a stack structure. The stack structure is cut along the first and second scribe line areas, passing the first and second openings.

摘要翻译： 一种封装半导体器件的方法。 提供了包括分别由划线区域分隔的多个管芯的衬底，其中至少一层覆盖衬底。 通过光刻和蚀刻去除划线部分内的层的一部分以形成开口。 沿着划线区域锯切基板，通过开口。 在替代实施例中，提供了包括分别由第一划线区域分开的多个第一裸片的第一衬底，其中至少一个第一结构层覆盖在第一衬底上。 图案化第一结构层以在第一划线区域内形成第一开口。 提供了包括分别由第二划线区域分开的多个第二裸片的第二衬底，其中至少一个第二结构层覆盖在衬底上。 图案化第二结构层以在第二划线区域内形成第二开口。 第一基板和第二基板被接合以形成堆叠结构。 沿着第一和第二划线区域切割堆叠结构，使第一和第二开口通过。

公开(公告)号：US20080224283A1

公开(公告)日：2008-09-18

申请号：US11523719

申请日：2006-09-20

申请人： Han-Ping Pu ,  Chien-Ping Huang

发明人： Han-Ping Pu ,  Chien-Ping Huang

IPC分类号： H01L23/495 ,  H01L21/60

CPC分类号： H01L24/13 ,  H01L23/3107 ,  H01L23/4334 ,  H01L23/4951 ,  H01L23/49548 ,  H01L24/14 ,  H01L24/17 ,  H01L2224/0401 ,  H01L2224/0603 ,  H01L2224/13099 ,  H01L2224/14 ,  H01L2224/1403 ,  H01L2224/141 ,  H01L2224/16 ,  H01L2224/16245 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014

摘要： A leadframe-based semiconductor package and a fabrication method thereof are provided. The leadframe-based semiconductor package includes a chip implanted with a plurality of first and second conductive bumps thereon, and a leadframe having a plurality of leads. The first conductive bumps are bonded to the leads to electrically connect the chip to the leadframe. The chip, the first and second conductive bumps, and the leadframe are encapsulated by an encapsulant, with bottom ends of the second conductive bumps and bottom surfaces of the leads being exposed from the encapsulant. This allows the second conductive bumps to provide additional input/output electrical connections for the chip besides the leads.

摘要翻译： 提供了一种引线框半导体封装及其制造方法。 基于引线框的半导体封装包括在其上注入多个第一和第二导电凸块的芯片以及具有多个引线的引线框架。 第一导电凸块被接合到引线以将芯片电连接到引线框架。 芯片，第一和第二导电凸块和引线框架由密封剂封装，第二导电凸块的底端和引线的底表面从密封剂暴露出来。 这允许第二导电凸块除了引线之外为芯片提供额外的输入/输出电连接。

公开(公告)号：US20070284710A1

公开(公告)日：2007-12-13

申请号：US11891926

申请日：2007-08-14

申请人： Chi-Chuan Wu ,  Chien-Ping Huang ,  Han-Ping Pu

发明人： Chi-Chuan Wu ,  Chien-Ping Huang ,  Han-Ping Pu

IPC分类号： H01L23/495 ,  H01L21/00

CPC分类号： H01L24/16 ,  H01L23/4951 ,  H01L23/49558 ,  H01L23/49575 ,  H01L2224/13099 ,  H01L2224/16245 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/351 ,  H01L2924/00

摘要： A flip-ship semiconductor package with a lead frame as a chip carrier is provided, wherein a plurality of leads of the lead frame are each formed with at least a dam member thereon. When a chip is mounted on the lead frame by means of solder bumps, each of the solder bumps is attached to the corresponding one of the leads at a position between the dam member and an inner end of the lead. During a reflow-soldering process for wetting the solder bumps to the leads, the dam members would help control collapse height of the solder bumps, so as to enhance resistance of the solder bumps to thermal stress generated by CTE (coefficient of thermal expansion) mismatch between the chip and the leads, thereby preventing incomplete electrical connection between the chip and the leads.

摘要翻译： 提供一种具有引线框架作为芯片载体的翻转半导体封装，其中引线框架的多个引线至少形成有至少一个阻挡构件。 当通过焊料凸块将芯片安装在引线框架上时，每个焊料凸块在引线的阻挡件和引线的内端之间的位置附接到相应的一个引线。 在用于将焊料凸点润湿到引线的回流焊接过程中，阻挡构件将有助于控制焊料凸块的塌陷高度，从而增强焊料凸块对CTE产生的热应力的阻力（热膨胀系数）不匹配 在芯片和引线之间，从而防止芯片和引线之间的不完全的电连接。

公开(公告)号：US07208825B2

公开(公告)日：2007-04-24

申请号：US11125886

申请日：2005-05-09

申请人： Han-Ping Pu ,  Chien Ping Huang

发明人： Han-Ping Pu ,  Chien Ping Huang

IPC分类号： H01L23/48 ,  H01L23/02 ,  H01L23/52 ,  H01L23/28 ,  H01L23/31

CPC分类号： H01L25/0657 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/24 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/16225 ,  H01L2224/24226 ,  H01L2224/24227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/1035 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01087 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00014

摘要： A semiconductor package and a fabrication method thereof are provided in which a chip is mounted on a substrate, and a dielectric layer is applied over the substrate and chip, with bond fingers formed on the substrate and electric contacts formed on the chip being exposed outside. A metal layer is formed over the dielectric layer and the exposed bond fingers and electric contacts, and patterned to form a plurality of conductive traces that electrically connect the electric contacts of the chip to the bond fingers of the substrate. The conductive traces replace conventional wire bonding technology and thus eliminate the occurrence of wire sweep or short circuits in fabrication processes. Therefore, a low profile chip with a reduced pitch between adjacent electric contacts can be used without being limited to feasibility of the wire bonding technology.

摘要翻译： 提供了一种半导体封装及其制造方法，其中芯片安装在基板上，并且电介质层被施加在基板和芯片上，具有形成在基板上的结合指状物，并且形成在芯片上的电触点暴露在外部。 在电介质层和暴露的结合指状物和电触点之上形成金属层，并且被图案化以形成将芯片的电触头电连接到衬底的结合指的多个导电迹线。 导电迹线取代了传统的引线键合技术，从而消除了制造工艺中线扫或短路的发生。 因此，可以使用在相邻的电触点之间具有减小的间距的低轮廓芯片，而不限于引线接合技术的可行性。

公开(公告)号：US07023085B2

公开(公告)日：2006-04-04

申请号：US10921582

申请日：2004-08-18

申请人： Han-Ping Pu

发明人： Han-Ping Pu

IPC分类号： H01L23/34

CPC分类号： H01L24/81 ,  H01L23/642 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/1403 ,  H01L2224/141 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16265 ,  H01L2224/1703 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19103 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/30105 ,  Y10S257/924 ,  H01L2924/00 ,  H01L2224/05599

摘要： A semiconductor package structure for improving electrical performance and a method for fabricating the same are proposed, in which a substrate having at least one pair of passive component pads is provided, wherein a semiconductor chip is attached on the substrate and a passive component is mounted to the passive component pads to locate between the substrate and the semiconductor chip. Thus, the passive component can electrically connect the chip and the substrate simultaneously without arranging an additional conductive trace layer, thereby improving the electrical performance of the semiconductor package structure and reducing the structure size.

摘要翻译： 提出了一种用于提高电性能的半导体封装结构及其制造方法，其中提供具有至少一对无源元件焊盘的衬底，其中半导体芯片附着在衬底上，并且将无源元件安装到 无源元件焊盘位于衬底和半导体芯片之间。 因此，无源部件可以同时电连接芯片和基板，而不需要设置附加的导电迹线层，从而提高半导体封装结构的电气性能并降低结构尺寸。