公开(公告)号：US20130119532A1

公开(公告)日：2013-05-16

申请号：US13294859

申请日：2011-11-11

申请人： Chun-Hung Lin ,  Yu-Feng Chen ,  Tsung-Shu Lin ,  Han-Ping Pu ,  Hsien-Wei Chen

发明人： Chun-Hung Lin ,  Yu-Feng Chen ,  Tsung-Shu Lin ,  Han-Ping Pu ,  Hsien-Wei Chen

IPC分类号： H01L23/485

CPC分类号： H01L24/14 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/525 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/0233 ,  H01L2224/02331 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05024 ,  H01L2224/0508 ,  H01L2224/05085 ,  H01L2224/05558 ,  H01L2224/05569 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/06131 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2224/1403 ,  H01L2224/14131 ,  H01L2224/14135 ,  H01L2224/14136 ,  H01L2224/14179 ,  H01L2224/16225 ,  H01L2224/17051 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/351 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2224/05552

摘要： A chip scale semiconductor device comprises a semiconductor die, a first bump and a second bump. The first bump having a first diameter and a first height is formed on an outer region of the semiconductor die. A second bump having a second diameter and a second height is formed on an inner region of the semiconductor die. The second diameter is greater than the first diameter while the second height is the same as the first height. By changing the shape of the bump, the stress and strain can be redistributed through the bump. As a result, the thermal cycling reliability of the chip scale semiconductor device is improved.

摘要翻译： 芯片级半导体器件包括半导体管芯，第一突起和第二突起。 具有第一直径和第一高度的第一凸块形成在半导体管芯的外部区域上。 具有第二直径和第二高度的第二凸起形成在半导体管芯的内部区域上。 第二直径大于第一直径，而第二高度与第一高度相同。 通过改变凸块的形状，应力和应变可通过凸块重新分布。 结果，提高了芯片级半导体器件的热循环可靠性。

公开(公告)号：US20120217632A1

公开(公告)日：2012-08-30

申请号：US13035586

申请日：2011-02-25

申请人： Yu-Feng Chen ,  Yuh Chern Shieh ,  Tsung-Shu Lin ,  Han-Ping Pu ,  Jiun Yi Wu ,  Tin-Hao Kuo

发明人： Yu-Feng Chen ,  Yuh Chern Shieh ,  Tsung-Shu Lin ,  Han-Ping Pu ,  Jiun Yi Wu ,  Tin-Hao Kuo

IPC分类号： H01L23/498

CPC分类号： H01L24/16 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/17 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16013 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00013 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599

摘要： A device includes a work piece, and a metal trace on a surface of the work piece. A Bump-on-Trace (BOT) is formed at the surface of the work piece. The BOT structure includes a metal bump, and a solder bump bonding the metal bump to a portion of the metal trace. The metal trace includes a metal trace extension not covered by the solder bump.

摘要翻译： 一种装置包括工件和工件表面上的金属迹线。 在工件的表面形成凸起跟踪（BOT）。 BOT结构包括金属凸块和将金属凸块接合到金属迹线的一部分的焊料凸块。 金属迹线包括未被焊料凸块覆盖的金属迹线延伸。

公开(公告)号：US08970033B2

公开(公告)日：2015-03-03

申请号：US13035586

申请日：2011-02-25

申请人： Yu-Feng Chen ,  Yuh Chern Shieh ,  Tsung-Shu Lin ,  Han-Ping Pu ,  Jiun Yi Wu ,  Tin-Hao Kuo

发明人： Yu-Feng Chen ,  Yuh Chern Shieh ,  Tsung-Shu Lin ,  Han-Ping Pu ,  Jiun Yi Wu ,  Tin-Hao Kuo

IPC分类号： H01L23/498 ,  H01L23/00

CPC分类号： H01L24/16 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/17 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16013 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00013 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599

摘要： A device includes a work piece, and a metal trace on a surface of the work piece. A Bump-on-Trace (BOT) is formed at the surface of the work piece. The BOT structure includes a metal bump, and a solder bump bonding the metal bump to a portion of the metal trace. The metal trace includes a metal trace extension not covered by the solder bump.

摘要翻译： 一种装置包括工件和工件表面上的金属迹线。 在工件的表面形成凸起跟踪（BOT）。 BOT结构包括金属凸块和将金属凸块接合到金属迹线的一部分的焊料凸块。 金属迹线包括未被焊料凸块覆盖的金属迹线延伸。

公开(公告)号：US09978656B2

公开(公告)日：2018-05-22

申请号：US13406270

申请日：2012-02-27

申请人： Tsung-Shu Lin ,  Han-Ping Pu ,  Ming-Da Cheng ,  Chang-Chia Huang ,  Hao-Juin Liu

发明人： Tsung-Shu Lin ,  Han-Ping Pu ,  Ming-Da Cheng ,  Chang-Chia Huang ,  Hao-Juin Liu

IPC分类号： H01L23/00 ,  H01L23/29 ,  H01L23/31 ,  H01L21/56

CPC分类号： H01L23/293 ,  H01L21/568 ,  H01L23/3157 ,  H01L24/02 ,  H01L24/03 ,  H01L24/04 ,  H01L24/05 ,  H01L24/06 ,  H01L24/10 ,  H01L24/11 ,  H01L24/12 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/0346 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/05541 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/10126 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/1181 ,  H01L2224/1191 ,  H01L2224/13005 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13083 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/16237 ,  H01L2224/73104 ,  H01L2224/81193 ,  H01L2224/81411 ,  H01L2224/81413 ,  H01L2224/81416 ,  H01L2224/81439 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/206 ,  H01L2924/207 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/05552

摘要： The mechanisms of forming a copper post structures described enable formation of copper post structures on a flat conductive surface. In addition, the copper post structures are supported by a molding layer with a Young's modulus (or a harder material) higher than polyimide. The copper post structures formed greatly reduce the risk of cracking of passivation layer and delamination of at the dielectric interface surrounding the copper post structures.

公开(公告)号：US20130127040A1

公开(公告)日：2013-05-23

申请号：US13302059

申请日：2011-11-22

申请人： Tsung-Shu Lin ,  Yu-Ling Tsai ,  Han-Ping Pu

发明人： Tsung-Shu Lin ,  Yu-Ling Tsai ,  Han-Ping Pu

IPC分类号： H01L23/485 ,  B23K1/00 ,  B23K1/20 ,  B23K31/12

CPC分类号： H01L25/105 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/1017 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00012

摘要： A package-on-package arrangement for maintaining die alignment during a reflow operation is provided. A first top die has a first arrangement of solder bumps. A bottom package has a first electrical arrangement to electrically connect to the first arrangement of solder bumps. A die carrier has a plurality of mounting regions defined on its bottom surface, wherein the first top die is adhered to the die carrier at a first of the plurality of mounting regions. One of a second top die and a dummy die having a second arrangement of solder bumps is also fixed to the die carrier at a second of the plurality of mounting regions of the die carrier. The first and second arrangements of solder bumps are symmetric to one another, therein balancing a surface tension during a reflow operation, and generally fixing an orientation of the die carrier with respect to the bottom package.

摘要翻译： 提供了一种用于在回流操作期间维持管芯对准的封装封装布置。 第一顶模具有焊料凸块的第一布置。 底部封装具有电连接到第一焊料凸点布置的第一电气布置。 模具载体具有限定在其底表面上的多个安装区域，其中第一顶模在多个安装区域中的第一个处粘附到模具载体。 具有第二排列焊料凸点的第二顶模和虚模具之一也在模具载体的多个安装区域的第二位置处固定到模具载体。 焊料凸块的第一和第二布置彼此对称，其中在回流操作期间平衡表面张力，并且通常相对于底部封装固定模具载体的取向。

公开(公告)号：US07871860B1

公开(公告)日：2011-01-18

申请号：US12620321

申请日：2009-11-17

申请人： Han-Ping Pu ,  Tsung-Shu Lin ,  Chen-Shien Chen

发明人： Han-Ping Pu ,  Tsung-Shu Lin ,  Chen-Shien Chen

IPC分类号： H01L21/00 ,  H01L21/50 ,  H01L21/48 ,  H01L21/44 ,  H01L21/46

CPC分类号： H01L24/81 ,  H01L21/563 ,  H01L24/16 ,  H01L2224/73203 ,  H01L2224/81211 ,  H01L2224/81801 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/351 ,  H01L2924/00

摘要： The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a chip and a substrate. The method also includes bonding the chip to the substrate. The method also includes, after the bonding the chip, dispensing a sealing material between the chip and the substrate. In accordance with the method, the chip and the substrate are maintained within a temperature range from the bonding the chip to the dispensing the sealing material, and wherein a lower limit of the temperature range is approximately twice a room temperature.

摘要翻译： 本公开提供了制造半导体器件的方法。 该方法包括提供芯片和基板。 该方法还包括将芯片接合到衬底。 该方法还包括在粘合芯片之后，在芯片和基板之间分配密封材料。 根据该方法，将芯片和基板保持在从接合芯片到分配密封材料的温度范围内，并且其中温度范围的下限约为室温的两倍。

公开(公告)号：US08927333B2

公开(公告)日：2015-01-06

申请号：US13302059

申请日：2011-11-22

申请人： Tsung-Shu Lin ,  Yu-Ling Tsai ,  Han-Ping Pu

发明人： Tsung-Shu Lin ,  Yu-Ling Tsai ,  Han-Ping Pu

IPC分类号： H01L21/00 ,  H01L21/76 ,  H01L23/48 ,  H01L23/552 ,  H01L25/10

CPC分类号： H01L25/105 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/1017 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00012

摘要： A package-on-package arrangement for maintaining die alignment during a reflow operation is provided. A first top die has a first arrangement of solder bumps. A bottom package has a first electrical arrangement to electrically connect to the first arrangement of solder bumps. A die carrier has a plurality of mounting regions defined on its bottom surface, wherein the first top die is adhered to the die carrier at a first of the plurality of mounting regions. One of a second top die and a dummy die having a second arrangement of solder bumps is also fixed to the die carrier at a second of the plurality of mounting regions of the die carrier. The first and second arrangements of solder bumps are symmetric to one another, therein balancing a surface tension during a reflow operation, and generally fixing an orientation of the die carrier with respect to the bottom package.

摘要翻译： 提供了一种用于在回流操作期间维持管芯对准的封装封装布置。 第一顶模具有焊料凸块的第一布置。 底部封装具有电连接到第一焊料凸点布置的第一电气布置。 模具载体具有限定在其底表面上的多个安装区域，其中第一顶模在多个安装区域中的第一个处粘附到模具载体。 具有第二排列焊料凸点的第二顶模和虚模具之一也在模具载体的多个安装区域的第二位置处固定到模具载体。 焊料凸块的第一和第二布置彼此对称，其中在回流操作期间平衡表面张力，并且通常相对于底部封装固定模具载体的取向。

公开(公告)号：US20130277828A1

公开(公告)日：2013-10-24

申请号：US13450191

申请日：2012-04-18

申请人： Chang-Chia Huang ,  Tsung-Shu Lin ,  Han-Ping Pu ,  Yen-Liang Lin ,  Sheng-Hsiang Chiu

发明人： Chang-Chia Huang ,  Tsung-Shu Lin ,  Han-Ping Pu ,  Yen-Liang Lin ,  Sheng-Hsiang Chiu

IPC分类号： H01L23/498 ,  H01L21/50

CPC分类号： H01L24/16 ,  H01L23/49816 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81024 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2924/15311 ,  H01L2224/16225 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/0665

摘要： Methods and apparatus for a solder mask trench used in a bump-on-trace (BOT) structure to form a semiconductor package are disclosed. A solder mask layer is formed on a trace and on a substrate. An opening of the solder mask layer, called a solder mask trench, is formed to expose the trace on the substrate. The solder mask trench has a width about a size of a diameter of a solder bump. A solder bump is landed directly on the exposed trace to connect a chip to the trace by an interconnect. With the formation of the solder mask trench, the trace exposed in the solder mask trench have a better grab force, which reduces the trace peeling failure for the semiconductor package. A plurality of solder mask trench rings may be formed in a package.

摘要翻译： 公开了用于形成半导体封装的凸起跟踪（BOT）结构中的焊接掩模沟槽的方法和装置。 在迹线和基板上形成焊料掩模层。 形成焊料掩模层的开口，称为焊料掩模沟槽，以露出衬底上的迹线。 焊接掩模沟槽的宽度大约为焊料凸块的直径。 焊料凸块直接落在裸露的轨迹上，通过互连将芯片连接到轨迹。 通过焊接掩模沟槽的形成，在焊接掩模沟槽中暴露的迹线具有更好的抓取力，这减少了半导体封装的迹线剥离故障。 可以在封装中形成多个焊接掩模沟槽环。

公开(公告)号：US09887144B2

公开(公告)日：2018-02-06

申请号：US13227983

申请日：2011-09-08

申请人： Wen-Yi Lin ,  Yu-Chih Liu ,  Ming-Chih Yew ,  Tsung-Shu Lin ,  Bor-Rung Su ,  Jing Ruei Lu ,  Wei-Ting Lin

发明人： Wen-Yi Lin ,  Yu-Chih Liu ,  Ming-Chih Yew ,  Tsung-Shu Lin ,  Bor-Rung Su ,  Jing Ruei Lu ,  Wei-Ting Lin

IPC分类号： H01L23/10 ,  H01L23/16 ,  H01L23/36 ,  H01L21/56 ,  H01L23/00

CPC分类号： H01L23/10 ,  H01L21/563 ,  H01L23/16 ,  H01L23/36 ,  H01L24/16 ,  H01L24/32 ,  H01L24/33 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/29099 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00014

摘要： A ring structure for chip packaging comprises a frame portion adaptable to bond to a substrate and at least one corner portion. The frame portion surrounds a semiconductor chip and defines an inside opening, and the inside opening exposes a portion of a surface of the substrate. The at least one corner portion extends from a corner of the frame portion toward the chip, and the corner portion is free of a sharp corner.

公开(公告)号：US09548283B2

公开(公告)日：2017-01-17

申请号：US13542528

申请日：2012-07-05

申请人： Tsung-Shu Lin ,  Hung-Jui Kuo ,  Yi-Wen Wu

发明人： Tsung-Shu Lin ,  Hung-Jui Kuo ,  Yi-Wen Wu

IPC分类号： H01L29/49 ,  H01L23/00 ,  H01L23/538 ,  H01L25/10 ,  H01L23/31 ,  H01L25/16

CPC分类号： H01L24/73 ,  H01L23/3121 ,  H01L23/5389 ,  H01L25/105 ,  H01L25/16 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/107 ,  H01L2924/0002 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012

摘要： A package-on-package (PoP) device comprises a bottom package on a substrate and a first set of conductive elements coupling the bottom package and the substrate. The PoP device further comprises a top package over the bottom package and a redistribution layer coupling the top package to the substrate. A method of forming a PoP device comprises coupling a first package to a substrate; and forming a redistribution layer over the first package and a top surface of the substrate. The method further comprises coupling a second package to the redistribution layer, wherein the redistribution layer couples the second package to the substrate.

摘要翻译： 封装封装（PoP）器件包括在衬底上的底部封装和耦合底部封装和衬底的第一组导电元件。 PoP器件还包括在底部封装上的顶部封装以及将顶部封装耦合到衬底的再分配层。 形成PoP器件的方法包括将第一封装耦合到衬底; 以及在所述第一封装和所述衬底的顶表面上形成再分布层。 该方法还包括将第二包装物耦合到再分配层，其中再分配层将第二包装物耦合到基底。