公开(公告)号：US20140104937A1

公开(公告)日：2014-04-17

申请号：US14049844

申请日：2013-10-09

Applicant: Everspin Technologies, Inc.

Inventor： Thomas Andre ,  Syed M. Alam ,  Halbert S. Lin

IPC: G11C11/16

CPC classification number: G11C11/1675 ,  G06F12/0802 ,  G06F2212/222 ,  G11C7/00 ,  G11C7/1042 ,  G11C7/12 ,  G11C7/22 ,  G11C11/1673 ,  G11C11/1693 ,  G11C11/4076

Abstract: In some examples, a memory device is configured to receive a precharge command and an activate command. The memory device performs a first series of events related to the precharge command in response to receiving the precharge command and a second series of events related to the activate command in response to receiving the activate command. The memory device delays the start of the second series of events until the first series of events completes.

Abstract translation: 在一些示例中，存储器设备被配置为接收预充电命令和激活命令。 响应于接收到所述预充电命令，响应于接收到所述激活命令，所述存储器装置执行与所述预充电命令相关的第一系列事件和与所述激活命令相关的第二系列事件。 存储器件延迟第二系列事件的开始直到第一系列事件完成。

公开(公告)号：US20130128657A1

公开(公告)日：2013-05-23

申请号：US13633479

申请日：2012-10-02

Applicant: EVERSPIN TECHNOLOGIES, INC.

Inventor： Syed M. Alam ,  Thomas Andre ,  Chitra Subramanian

IPC: G11C11/16

CPC classification number: G11C11/1673 ,  G11C11/1675 ,  G11C13/004 ,  G11C2013/0057

Abstract: A method of reading data from a plurality of bits in a spin-torque magnetoresistive memory array includes performing one or more referenced read operations of the bits, and performing a self-referenced read operation, for example, a destructive self-referenced read operation, of any of the bits not successfully read by the referenced read operation. The referenced read operations can be initiated at the same time or prior to that of the destructive self-referenced read operation.

Abstract translation: 一种从自旋转矩磁阻存储器阵列中的多个位读取数据的方法包括执行一个或多个参考的比特的读取操作，以及执行自参考的读取操作，例如破坏性的自参考读取操作， 通过引用的读取操作未成功读取的任何位。 引用的读取操作可以在破坏性自引用读取操作的同一时间或之前启动。

公开(公告)号：US20130128650A1

公开(公告)日：2013-05-23

申请号：US13657002

申请日：2012-10-22

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. Alam ,  Thomas Andre

IPC: G11C11/00

CPC classification number: G11C11/1673 ,  G11C7/00 ,  G11C7/10 ,  G11C7/1084 ,  G11C7/12 ,  G11C11/00 ,  G11C11/02 ,  G11C11/16 ,  G11C11/1653 ,  G11C11/1675 ,  G11C13/004 ,  G11C13/0069 ,  G11C29/50008

Abstract: An analog read circuit measures the resistance of each of a plurality of bits in an array of resistive memory elements. Data stored within a latch determines whether to selectively enable the analog read circuit. In an alternate embodiment, a sense amplifier is coupled to the latch and the array, and the data stored in the latch determines whether to selectively enable the sense amplifier.

公开(公告)号：US11637235B2

公开(公告)日：2023-04-25

申请号：US16744963

申请日：2020-01-16

Applicant: Everspin Technologies, Inc.

Inventor： Sumio Ikegawa ,  Han Kyu Lee ,  Sanjeev Aggarwal ,  Jijun Sun ,  Syed M. Alam ,  Thomas Andre

IPC: H01L43/04 ,  H01L43/06 ,  H01L43/10 ,  H01L43/14 ,  H01L27/22

Abstract: The present disclosure is drawn to, among other things, a magnetoresistive device and a magnetoresistive memory comprising a plurality of such magnetoresistive devices. In some aspects, a magnetoresistive device may include a magnetically fixed region, a magnetically free region above or below the magnetically fixed region, and an intermediate region positioned between the magnetically fixed region and the magnetically free region, wherein the intermediate region includes a first dielectric material. The magnetoresistive device may also include encapsulation layers formed on opposing side walls of the magnetically free region, wherein the encapsulation layers include the first dielectric material.

公开(公告)号：US10199122B2

公开(公告)日：2019-02-05

申请号：US15852678

申请日：2017-12-22

Applicant: Everspin Technologies Inc.

Inventor： Thomas Andre ,  Jon Slaughter ,  Dimitri Houssameddine ,  Syed M. Alam

IPC: G06F7/02 ,  H03M13/00 ,  G11C29/50 ,  G11C11/16 ,  G06F11/08 ,  G06F11/10 ,  G11C29/04

Abstract: In some examples, a memory device may be configured to store data in either an original or an inverted state based at least in part on a state associated with one or more shorted bit cells. For instance, the memory device may be configured to identify a shorted bit cell within a memory array and to store the data in the memory array, such that a state of the data bit stored in the shorted bit cell matches the state associated with the shorted bit cell.

公开(公告)号：US10109333B2

公开(公告)日：2018-10-23

申请号：US15672469

申请日：2017-08-09

Applicant: EVERSPIN TECHNOLOGIES, INC.

Inventor： Thomas Andre

IPC: G11C13/00 ,  G11C5/06 ,  G11C11/56 ,  G11C11/419 ,  G11C11/16 ,  G06F11/10 ,  H01L43/08 ,  H01L43/02 ,  H01L27/22 ,  G11C29/52

Abstract: In some examples, a nonvolatile storage element may be configured to store a state or value during a low power or powered down period of a circuit. For example, the nonvolatile storage element may include a bridge of resistive elements that have a resistive state that may be configured by applying voltages to multiple drive paths. A sense amplifier may be connected to the bridge in order to resolve a voltage differential associated with the bridge to ether power or ground and, thereby determine the state associated with on the nonvolatile storage element.

公开(公告)号：US10103197B1

公开(公告)日：2018-10-16

申请号：US15650203

申请日：2017-07-14

Applicant: Everspin Technologies, Inc.

Inventor： Thomas Andre ,  Sanjeev Aggarwal ,  Kerry Joseph Nagel ,  Sarin A. Deshpande

IPC: H01L29/82 ,  H01L43/00 ,  H01L27/22 ,  H01L43/02 ,  H01L43/12 ,  H01L43/08

Abstract: Magnetoresistive device architectures and methods for manufacturing are presented that facilitate integration of process steps associated with forming such devices into standard process flows used for surrounding logic/circuitry. In some embodiments, the magnetoresistive device structures are designed such that the devices are able to fit within the vertical dimensions of the integrated circuit associated with a single metal layer and a single layer of interlayer dielectric material. Integrating the processing for the magnetoresistive devices can include using the same standard interlayer dielectric material as used in the surrounding circuits on the integrated circuit as well as using standard vias to interconnect to at least one of the electrodes of the magnetoresistive devices.

公开(公告)号：US09978433B2

公开(公告)日：2018-05-22

申请号：US15368871

申请日：2016-12-05

Applicant: Everspin Technologies, Inc.

Inventor： Thomas Andre

IPC: G11C7/00 ,  G11C11/16 ,  G11C7/20 ,  G11C29/02 ,  G11C14/00 ,  G06F12/02 ,  G11C29/04

CPC classification number: G11C11/1675 ,  G06F12/0238 ,  G06F12/0804 ,  G06F12/0871 ,  G06F2212/1032 ,  G06F2212/7203 ,  G11C7/20 ,  G11C11/1673 ,  G11C11/1693 ,  G11C14/00 ,  G11C29/023 ,  G11C29/028 ,  G11C2029/0407

Abstract: In some examples, a memory device is configured with non-volatile memory array(s) having one or more associated volatile memory arrays. The memory device may include a non-destructive write mode configured to prevent access to the non-volatile memory array(s) during an initiation or calibration sequence performed by the memory device or an electronic device associated with the memory device to calibrate read and write access timing associated with the memory device.

公开(公告)号：US09754652B2

公开(公告)日：2017-09-05

申请号：US15149826

申请日：2016-05-09

Applicant: Everspin Technologies, Inc.

Inventor： Thomas Andre

IPC: G11C13/00 ,  G11C11/56 ,  G11C11/419 ,  G11C11/16 ,  G06F11/10 ,  G11C29/52 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  G11C5/06

CPC classification number: G11C11/1673 ,  G06F11/1068 ,  G09C1/00 ,  G11C5/06 ,  G11C11/1659 ,  G11C11/1675 ,  G11C13/0002 ,  G11C13/0026 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C14/0081 ,  G11C14/009 ,  G11C29/52 ,  G11C2213/75 ,  G11C2213/77 ,  H01L27/228 ,  H01L43/02 ,  H01L43/08 ,  H04L9/0866

Abstract: In some examples, a nonvolatile storage element may be configured to store a state or value during a low power or powered down period of a circuit. For example, the nonvolatile storage element may include a bridge of resistive elements that have a resistive state that may be configured by applying voltages to multiple drive paths. A sense amplifier may be connected to the bridge in order to resolve a voltage differential associated with the bridge to either power or ground and, thereby determine the state associated with on the nonvolatile storage element.

公开(公告)号：US09740431B2

公开(公告)日：2017-08-22

申请号：US15212271

申请日：2016-07-17

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. Alam ,  Thomas Andre ,  Dietmar Gogl

IPC: G11C11/00 ,  G06F3/06 ,  G11C7/10 ,  G11C11/4076 ,  G11C8/04 ,  G06F12/02 ,  G06F12/06 ,  G11C11/16 ,  G11C11/4094 ,  G11C11/4096 ,  G11C14/00 ,  G06F13/16 ,  G11C11/4091

CPC classification number: G06F3/0659 ,  G06F3/0611 ,  G06F3/0685 ,  G06F12/0246 ,  G06F12/0638 ,  G06F13/1694 ,  G06F2212/205 ,  G06F2212/7201 ,  G11C7/1042 ,  G11C7/1072 ,  G11C8/04 ,  G11C11/005 ,  G11C11/16 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096 ,  G11C14/0036

Abstract: A memory system and memory controller for interleaving volatile and non-volatile memory accesses are described. In the memory system, the memory controller is coupled to the volatile and non-volatile memories using a shared address bus. Activate latencies for the volatile and non-volatile memories are different, and registers are included on the memory controller for storing latency values. Additional registers on the memory controller store precharge latencies for the memories as well as page size for the non-volatile memory. A memory access sequencer on the memory controller asserts appropriate chip select signals to the memories to initiate operations therein.