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102 条记录 (耗时 0.037 秒)

    Method and system for distributed video compression in personal computer architecture
    83.
    发明授权
    Method and system for distributed video compression in personal computer architecture 失效

    公开(公告)号：US06411651B1

    公开(公告)日：2002-06-25

    申请号：US09105059

    申请日：1998-06-26

    申请人： Robert C. Rose ,  Matthew J. Adiletta ,  Samuel W. Ho

    发明人： Robert C. Rose ,  Matthew J. Adiletta ,  Samuel W. Ho

    IPC分类号： H04N712

    CPC分类号： H04N21/4143 ,  H04N19/42 ,  H04N19/61

    摘要： A method and system for compressing video data in a computer has video processing that is distributed between preprocessing hardware in a video capture/controller card and a central processing unit of the computer. Frames of video data are passed to a motion estimation unit of the preprocessing hardware. This unit generates motion information describing inter-frame changes in the video data. Next, motion-compensated temporal filtering is performed on the frames of video data using the motion information. A video frame processing unit of the controller card, used for processing video data to the monitor, is reused for the temporal filtering of the input video data. Finally, the temporally-filtered video data is passed to the central processing unit, which performs inter-frame and/or intra-frame compression with reference to the motion information. In this way, motion-compensated temporal filtering is performed, thus removing the associated noise without adding to the CPU's processing burden, but the costs associated with dedicated compression hardware are avoided by relying on the video capture capabilities in the video controller card.

    Method and apparatus for eliminating the transpose buffer during a decomposed forward or inverse 2-dimensional discrete cosine transform through operand decomposition storage and retrieval
    84.
    发明授权
    Method and apparatus for eliminating the transpose buffer during a decomposed forward or inverse 2-dimensional discrete cosine transform through operand decomposition storage and retrieval 失效
    在通过操作数分解存储和检索分解的正向或反向2维离散余弦变换中消除转置缓冲器的方法和装置

    公开(公告)号：US6026217A

    公开(公告)日：2000-02-15

    申请号：US668480

    申请日：1996-06-21

    申请人： Matthew J. Adiletta

    发明人： Matthew J. Adiletta

    IPC分类号： H04N7/26 ,  H04N7/50 ,  H04N1/00 ,  H04N1/41

    CPC分类号： H04N19/423 ,  H04N19/126 ,  H04N19/14 ,  H04N19/152 ,  H04N19/159 ,  H04N19/169 ,  H04N19/176 ,  H04N19/177 ,  H04N19/192 ,  H04N19/42 ,  H04N19/61 ,  H04N19/149 ,  H04N19/15

    摘要： A method and apparatus is presented for video image compression using a unique operand decomposition technique combined with an innovative data scatter and retrieve process. This combination of features allows the use of single ported RAM structures where multiported RAMS would normally be used, such as when retrieving two operands in the same time cycle. As applied to the Discrete Cosine Transformation this method and apparatus additionally allows elimination of the usual prior art use of a separate transpose matrix buffer. The elimination of the separate transpose matrix buffer is accomplished by combining the transpose matrix intermediate results memory storage with the memory buffer used for the other intermediate results in a double buffer system. The double buffer memory locations are chosen so that the intermediate storage register address are orthogonal to the initial source addresses, thereby using one of the properties of the Discrete Cosine Transform to improve speed of operation and reduce the circuit area and system cost.

    摘要翻译： 提出了一种使用独特的操作数分解技术结合创新的数据分散和检索过程进行视频图像压缩的方法和装置。 这种特征的组合允许使用通常使用多端口RAMS的单端口RAM结构，例如在相同时间周期中检索两个操作数时。 如应用于离散余弦变换，该方法和装置另外允许消除通常的现有技术使用单独的转置矩阵缓冲器。 通过将转置矩阵中间结果存储器存储器与用于另一中间结果的存储器缓冲器组合在双缓冲器系统中来实现单独的转置矩阵缓冲器的消除。 选择双缓冲存储器位置，使得中间存储寄存器地址与初始源地址正交，从而使用离散余弦变换的特性之一来提高操作速度并减少电路面积和系统成本。

    High speed parallel multiplier circuit
    85.
    发明授权
    High speed parallel multiplier circuit 失效
    高速并联电路

    公开(公告)号：US5159568A

    公开(公告)日：1992-10-27

    申请号：US124926

    申请日：1987-11-24

    申请人： Matthew J. Adiletta ,  Stephen C. Root

    发明人： Matthew J. Adiletta ,  Stephen C. Root

    IPC分类号： G06F7/53 ,  G06F7/506 ,  G06F7/508 ,  G06F7/52

    CPC分类号： G06F7/5318

    摘要： The binary multiplier circuit for obtaining a product of a M-bit multiplier and a N-bit multiplicand includes a multiplier circuit which produces a matrix of original summand bits having M rows and M+N columns and a matrix reduction circuit. In the matrix reduction circuit, for every column of the matrix having three or more original summand bits, groups of three bits are input into full adder circuits which output a sum bit for that column and a carry bit for the column in the next most significant bit position. For every column having three or fewer original summand bits, and having the least significant column position that is not yet reduced to two or fewer bits, groups of two bits are input into a half adder circuit which outputs a sum bit for that column and carry bit for a column in the next most significant bit position. Iterative reductions are performed for each column by using full adder circuits for every group of three bits in a column and by using a half adder circuit for any remaining group of two bits in a column. The reduction continues until each column of the matrix is reduced to two or fewer bits. The remaining two rows of bits can be input to a carry-propagating adder circuit to output a sum equal to the product.

    CABLELESS CONNECTION APPARATUS AND METHOD FOR COMMUNICATION BETWEEN CHASSIS
    88.
    发明申请
    CABLELESS CONNECTION APPARATUS AND METHOD FOR COMMUNICATION BETWEEN CHASSIS 有权
    无线连接装置和组合之间的通信方法

    公开(公告)号：US20150288410A1

    公开(公告)日：2015-10-08

    申请号：US14244475

    申请日：2014-04-03

    申请人： Matthew J. Adiletta ,  Aaron Gorius ,  Myles Wilde ,  Hugh Wilkinson ,  Amit Y. Kumar

    发明人： Matthew J. Adiletta ,  Aaron Gorius ,  Myles Wilde ,  Hugh Wilkinson ,  Amit Y. Kumar

    IPC分类号： H04B1/40 ,  H04L12/931 ,  H04L29/08 ,  H04L12/933

    CPC分类号： H04L49/10 ,  H04B1/40 ,  H04L49/35 ,  H04L67/10 ,  H05K7/1492

    摘要： Apparatus and methods for cableless connection of components within chassis and between separate chassis. Pairs of Extremely High Frequency (EHF) transceiver chips supporting very short length millimeter-wave wireless communication links are configured to pass radio frequency signals through holes in one or more metal layers in separate chassis and/or frames, enabling components in the separate chassis to communicate without requiring cables between the chassis. Various configurations are disclosed, including multiple configurations for server chassis, storage chassis and arrays, and network/switch chassis. The EHF-based wireless links support link bandwidths of up to 6 gigabits per second, and may be aggregated to facilitate multi-lane links.

    摘要翻译： 用于无线连接机箱内部和分离机箱之间的部件的装置和方法。 支持非常短长度的毫米波无线通信链路的极高频（EHF）收发器芯片配置成通过单独的机箱和/或框架中的一个或多个金属层中的孔传递射频信号，使单独机架中的组件能够 通信而不需要机箱之间的电缆。 公开了各种配置，包括服务器机箱，存储机箱和阵列以及网络/交换机机箱的多种配置。 基于EHF的无线链路支持高达每秒6吉比特的链路带宽，并且可以聚合以便于多车道链路。

    Multi-threaded sequenced receive for fast network port stream of packets
    90.
    发明授权
    Multi-threaded sequenced receive for fast network port stream of packets 失效
    多线程排序接收快速网络端口流数据包

    公开(公告)号：US06952824B1

    公开(公告)日：2005-10-04

    申请号：US09710439

    申请日：2000-11-10

    申请人： Donald F. Hooper ,  Matthew J. Adiletta ,  Gilbert M. Wolrich

    发明人： Donald F. Hooper ,  Matthew J. Adiletta ,  Gilbert M. Wolrich

    IPC分类号： G06F9/46

    CPC分类号： G06F9/546 ,  G06F9/3851 ,  G06F9/3885 ,  G06F9/485 ,  G06F9/4881 ,  G06F9/544

    摘要： A method of processing network data in a network processor includes using three or more threads to process a beginning portion, a middle portion, and an end portion of data packet. The first thread processes the beginning portion; one or more middle threads process the middle portion, and a last thread processes the end portion. First information is indirectly passed from the first thread to the last thread via a first buffer with the middle threads progressively updating the first information. Second information is directly passed from the first thread to the last thread via a second buffer.

    摘要翻译： 一种在网络处理器中处理网络数据的方法包括使用三个或更多个线程来处理数据分组的开始部分，中间部分和结束部分。 第一个线程处理起始部分; 一个或多个中间线程处理中间部分，最后一个线程处理端部。 第一个信息通过第一个缓冲区从第一个线程间接传递到最后一个线程，中间线程逐渐更新第一个信息。 第二个信息通过第二个缓冲区从第一个线程直接传递到最后一个线程。