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    COMPUTER PROGRAM PRODUCTS FOR DETERMINING STOPPING POWERS OF DESIGN STRUCTURES WITH RESPECT TO A TRAVELING PARTICLE
    83.
    发明申请
    COMPUTER PROGRAM PRODUCTS FOR DETERMINING STOPPING POWERS OF DESIGN STRUCTURES WITH RESPECT TO A TRAVELING PARTICLE 有权
    计算机程序产品用于确定相对于旅行颗粒的设计结构的停止功能

    公开(公告)号：US20080201681A1

    公开(公告)日：2008-08-21

    申请号：US12111529

    申请日：2008-04-29

    申请人： Giovanni Fiorenza ,  Conal E. Murray ,  Kenneth P. Rodbell ,  Henry Tang

    发明人： Giovanni Fiorenza ,  Conal E. Murray ,  Kenneth P. Rodbell ,  Henry Tang

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5009 ,  G06F2217/16

    摘要： A computer program product, comprising a computer usable medium having a computer readable program code embodied therein, said computer readable program code including an algorithm adapted to implement a method including the following steps. First, design information of the design structure is provided including a back-end-of-line layer of the integrated circuit which includes N interconnect layers, N being a positive integer. Next, each interconnect layer of the N interconnect layers is divided into multiple pixels. Next, a first path of a traveling particle in a first interconnect layer of the N interconnect layers is determined. Next, M path pixels of the multiple pixels of the first interconnect layer on the first path of the traveling particle are identified, M being a positive integer. Next, a first loss energy lost by the traveling particle due to its completely passing through a first pixel of the M path pixels is determined.

    摘要翻译： 一种计算机程序产品，包括具有包含在其中的计算机可读程序代码的计算机可用介质，所述计算机可读程序代码包括适于实现包括以下步骤的方法的算法。 首先，提供设计结构的设计信息，其包括包括N个互连层的集成电路的后端行层，N是正整数。 接下来，N个互连层的每个互连层被分成多个像素。 接下来，确定N个互连层的第一互连层中的行进粒子的第一路径。 接下来，识别行进粒子的第一路径上的第一互连层的多个像素的M个路径像素，M是正整数。 接下来，确定由于行进粒子完全通过M路径像素的第一像素而损失的第一损失能量。

    Homogeneous Copper Interconnects for BEOL
    85.
    发明申请
    Homogeneous Copper Interconnects for BEOL 审中-公开
    BEOL的均匀铜互连

    公开(公告)号：US20080156636A1

    公开(公告)日：2008-07-03

    申请号：US11971488

    申请日：2008-01-09

    申请人： Kevin S. Petrarca ,  Mahadevaiyer Krishnan ,  Michael Lofaro ,  Kenneth P. Rodbell

    发明人： Kevin S. Petrarca ,  Mahadevaiyer Krishnan ,  Michael Lofaro ,  Kenneth P. Rodbell

    IPC分类号： C23C14/16

    CPC分类号： H01L21/76873 ,  H01L21/2855 ,  H01L21/7684 ,  H01L21/76877

    摘要： Defects on the edge of copper interconnects for back end of the line semiconductor devices are alleviated by an interconnect that comprises an impure copper seed layer. The impure copper seed layer covers a barrier layer, which covers an insulating layer that has an opening. Electroplated copper fills the opening in the insulating layer. Through a chemical mechanical polish, the barrier layer, the impure an impure copper seed layer derived from an electroplated copper bath copper seed layer, and the electroplated copper are planarized to the insulating layer.

    摘要翻译： 通过包括不纯铜种子层的互连可以减轻线半导体器件后端的铜互连边缘的缺陷。 不纯铜种子层覆盖阻挡层，其覆盖具有开口的绝缘层。 电镀铜填充绝缘层中的开口。 通过化学机械抛光，阻挡层，不纯的由电镀铜浴铜籽晶层衍生的铜籽晶层和电镀铜平坦化到绝缘层。

    Method for plating copper conductors and devices formed
    89.
    发明授权
    Method for plating copper conductors and devices formed 有权
    电镀铜导体和器件的方法

    公开(公告)号：US06344129B1

    公开(公告)日：2002-02-05

    申请号：US09418197

    申请日：1999-10-13

    申请人： Kenneth P. Rodbell ,  Panayotis C. Andricacos ,  Cyril Cabral, Jr. ,  Lynne M. Gignac ,  Cyprian E. Uzoh ,  Peter S. Locke

    发明人： Kenneth P. Rodbell ,  Panayotis C. Andricacos ,  Cyril Cabral, Jr. ,  Lynne M. Gignac ,  Cyprian E. Uzoh ,  Peter S. Locke

    IPC分类号： C25D500

    CPC分类号： C25D5/10 ,  C25D3/38 ,  C25D5/00 ,  C25D7/123 ,  C25D21/02 ,  H05K3/423

    摘要： A method for plating copper conductors on an electronic substrate and devices formed are disclosed. In the method, an electroplating copper bath that is filled with an electroplating solution kept at a temperature between about 0° C. and about 18° C. is first provided. A copper layer on the electronic substrate immersed in the electroplating solution is then plated either in a single step or in a dual-step deposition process. The dual-step deposition process is more suitable for depositing copper conductors in features that have large aspect ratios, such as a via hole in a dual damascene structure having an aspect ratio of diameter/depth of more than ⅓ or as high as {fraction (1/10)}. Various electroplating parameters are utilized to provide a short resistance transient in either the single step deposition or the dual-step deposition process. These parameters include the bath temperature, the bath agitation, the additive concentration in the plating bath, the plating current density utilized, the deposition rate of the copper film and the total thickness of the copper film deposited.

    摘要翻译： 公开了一种在电子基板上镀铜导体的方法和形成的器件。 在该方法中，首先提供填充有保持在约0℃至约18℃之间的温度的电镀溶液的电镀铜浴。 然后将浸在电镀溶液中的电子基板上的铜层以单步骤或双步沉积工艺进行镀覆。 双步沉积方法更适合于在具有大纵横比的特征中沉积铜导体，例如双镶嵌结构中的通孔，其直径/深度的纵横比大于1/3或高达{分数（ 1/10）}。 各种电镀参数用于在单步沉积或双步沉积工艺中提供短电阻瞬变。 这些参数包括浴温度，浴液搅拌，镀浴中的添加剂浓度，所用的电镀电流密度，铜膜的沉积速率和沉积的铜膜的总厚度。