公开(公告)号：US20190103556A1

公开(公告)日：2019-04-04

申请号：US16200969

申请日：2018-11-27

Applicant: Micron Technology, Inc.

Inventor： Jun Liu ,  Kunal R. Parekh

IPC: H01L45/00 ,  H01L43/12 ,  H01L43/08 ,  H01L43/02 ,  H01L27/24 ,  H01L21/768 ,  H01L21/033

CPC classification number: H01L45/16 ,  H01L21/0337 ,  H01L21/76807 ,  H01L21/76816 ,  H01L27/2472 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/126 ,  H01L45/1273 ,  H01L45/14 ,  H01L45/146 ,  H01L45/147 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Electrical contacts may be formed by forming dielectric liners along sidewalls of a dielectric structure, forming sacrificial liners over and transverse to the dielectric liners along sidewalls of a sacrificial structure, selectively removing portions of the dielectric liners at intersections of the dielectric liners and sacrificial liners to form pores, and at least partially filling the pores with a conductive material. Nano-scale pores may be formed by similar methods. Bottom electrodes may be formed and electrical contacts may be structurally and electrically coupled to the bottom electrodes to form memory devices. Nano-scale electrical contacts may have a rectangular cross-section of a first width and a second width, each width less than about 20 nm. Memory devices may include bottom electrodes, electrical contacts having a cross-sectional area less than about 150 nm2 over and electrically coupled to the bottom electrodes, and a cell material over the electrical contacts.

公开(公告)号：US10229923B2

公开(公告)日：2019-03-12

申请号：US15818338

申请日：2017-11-20

Applicant: Micron Technology, Inc.

Inventor： Justin B. Dorhout ,  Kunal R. Parekh ,  Martin C. Roberts ,  Mohd Kamran Akhtar ,  Chet E. Carter ,  David Daycock

IPC: H01L27/11551 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/1157

Abstract: Some embodiments include an integrated assembly with a semiconductor channel material having a boundary region where a more-heavily-doped region interfaces with a less-heavily-doped region. The more-heavily-doped region and the less-heavily-doped region have the same majority carriers. The integrated assembly includes a gating structure adjacent the semiconductor channel material and having a gating region and an interconnecting region of a common and continuous material. The gating region has a length extending along a segment of the more-heavily-doped region, a segment of the less-heavily-doped region, and the boundary region. The interconnecting region extends laterally outward from the gating region on a side opposite the semiconductor channel region, and is narrower than the length of the gating region. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20180076209A1

公开(公告)日：2018-03-15

申请号：US15818338

申请日：2017-11-20

Applicant: Micron Technology, Inc.

Inventor： Justin B. Dorhout ,  Kunal R. Parekh ,  Martin C. Roberts ,  Mohd Kamran Akhtar ,  Chet E. Carter ,  David Daycock

IPC: H01L27/11551 ,  H01L27/11524

CPC classification number: H01L27/11524 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582

Abstract: Some embodiments include an integrated assembly with a semiconductor channel material having a boundary region where a more-heavily-doped region interfaces with a less-heavily-doped region. The more-heavily-doped region and the less-heavily-doped region are majority doped with a same dopant type. The integrated assembly includes a gating structure adjacent the semiconductor channel material and having a gating region and an interconnecting region of a common and continuous material. The gating region has a length extending across a segment of the more-heavily-doped region, a segment of the less-heavily-doped region, and the boundary region. The interconnecting region extends outwardly from the gating region on a side opposite the semiconductor channel region, and is narrower than the length of the gating region. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20170301685A1

公开(公告)日：2017-10-19

申请号：US15133119

申请日：2016-04-19

Applicant: Micron Technology, Inc.

Inventor： Justin B. Dorhout ,  Fei Wang ,  Chet E. Carter ,  Ian Laboriante ,  John D. Hopkins ,  Kunal Shrotri ,  Ryan Meyer ,  Vinayak Shamanna ,  Kunal R. Parekh ,  Martin C. Roberts ,  Matthew Park

IPC: H01L27/115 ,  H01L23/532 ,  H01L23/528

CPC classification number: H01L27/11582 ,  H01L23/528 ,  H01L23/53257 ,  H01L27/1157

Abstract: Some embodiments include an integrated structure having vertically-stacked conductive levels alternating with dielectric levels. A layer over the conductive levels includes silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus. In some embodiments the vertically-stacked conductive levels are wordline levels within a NAND memory array. Some embodiments include an integrated structure having vertically-stacked conductive levels alternating with dielectric levels. Vertically-stacked NAND memory cells are along the conductive levels within a memory array region. A staircase region is proximate the memory array region. The staircase region has electrical contacts in one-to-one correspondence with the conductive levels. A layer is over the memory array region and over the staircase region. The layer includes silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus.

公开(公告)号：US09356145B2

公开(公告)日：2016-05-31

申请号：US14456435

申请日：2014-08-11

Applicant: Micron Technology, Inc.

Inventor： Gurtej S. Sandhu ,  Kunal R. Parekh

IPC: H01L29/76 ,  H01L29/78 ,  H01L29/10 ,  H01L21/28 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L21/8238

CPC classification number: H01L29/4983 ,  H01L21/28114 ,  H01L21/823437 ,  H01L21/823456 ,  H01L21/823468 ,  H01L21/823807 ,  H01L21/823828 ,  H01L29/1033 ,  H01L29/1054 ,  H01L29/401 ,  H01L29/42376 ,  H01L29/6656 ,  H01L29/66659 ,  H01L29/7843 ,  H01L29/7845 ,  Y10S257/90

Abstract: The use of strained gate electrodes in integrated circuits results in a transistor having improved carrier mobility, improved drive characteristics, and reduced source drain junction leakage. The gate electrode strain can be obtained through non symmetric placement of stress inducing structures as part of the gate electrode.

Abstract translation: 在集成电路中使用应变栅电极导致晶体管具有改善的载流子迁移率，改进的驱动特性和减少的源极漏极结泄漏。 栅电极应变可以通过不对称放置应力诱导结构作为栅电极的一部分获得。

公开(公告)号：US20140252562A1

公开(公告)日：2014-09-11

申请号：US14154329

申请日：2014-01-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kyle K. Kirby ,  Kunal R. Parekh

IPC: H01L23/48

CPC classification number: H01L25/0657 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/16 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/06181 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: Semiconductor substrates with unitary vias and via terminals, and associated systems and methods are disclosed. A representative method in accordance with a particular embodiment includes forming a blind via in a semiconductor substrate, applying a protective layer to a sidewall surface of the via, and forming a terminal opening by selectively removing substrate material from an end surface of the via, while protecting from removal substrate material against which the protective coating is applied. The method can further include disposing a conductive material in both the via and the terminal opening to form an electrically conductive terminal that is unitary with conductive material in the via. Substrate material adjacent to the terminal can then be removed to expose the terminal, which can then be connected to a conductive structure external to the substrate.

Abstract translation: 公开了具有单一通孔和通孔端子的半导体衬底以及相关联的系统和方法。 根据特定实施例的代表性方法包括在半导体衬底中形成盲通孔，将保护层施加到通孔的侧壁表面，以及通过从通孔的端面选择性地去除衬底材料形成端子开口，同时 防止施加保护涂层的去除衬底材料。 该方法还可以包括在导通孔和端子开口中设置导电材料，以形成与通路中的导电材料整体的导电端子。 然后可以除去与端子相邻的衬底材料以露出端子，然后该端子可以连接到衬底外部的导电结构。

公开(公告)号：US20140097499A1

公开(公告)日：2014-04-10

申请号：US14105595

申请日：2013-12-13

Applicant: Micron Technology, Inc.

Inventor： Kunal R. Parekh ,  John K. Zahurak

IPC: H01L29/06 ,  H01L27/088

CPC classification number: H01L29/0653 ,  H01L21/2815 ,  H01L21/3086 ,  H01L21/3088 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/108 ,  H01L27/10876 ,  H01L27/10891 ,  H01L29/0649 ,  H01L29/4236 ,  H01L29/66621 ,  H01L29/66795

Abstract: Methods of pitch doubling of asymmetric features and semiconductor structures including the same are disclosed. In one embodiment, a single photolithography mask may be used to pitch double three features, for example, of a DRAM array. In one embodiment, two wordlines and a grounded gate over field may be pitch doubled. Semiconductor structures including such features are also disclosed.

Abstract translation: 公开了不对称特征和包括其的半导体结构的间距倍增方法。 在一个实施例中，可以使用单个光刻掩模来扩展例如DRAM阵列的三重特征。 在一个实施例中，两个字线和接地栅极可以是倍频。 还公开了包括这些特征的半导体结构。

公开(公告)号：US20250167072A1

公开(公告)日：2025-05-22

申请号：US19029881

申请日：2025-01-17

Applicant: Micron Technology, Inc.

Inventor： Kunal R. Parekh ,  Angela S. Parekh

IPC: H01L23/373 ,  H01L23/00 ,  H01L23/367 ,  H01L25/065 ,  H01L25/18

Abstract: A semiconductor device assembly is provided. The assembly includes a first semiconductor device including a plurality of electrical contacts on an upper surface thereof; a monolithic silicon structure having a lower surface in contact with the upper surface of the first semiconductor device, the monolithic silicon structure including a cavity extending from the lower surface completely through a body of the monolithic silicon structure to a top surface of the monolithic silicon structure; and a second semiconductor device disposed in the cavity, the second semiconductor device including a plurality of interconnects, each operatively coupled to a corresponding one of the plurality of electrical contacts.

公开(公告)号：US20250149382A1

公开(公告)日：2025-05-08

申请号：US19019070

申请日：2025-01-13

Applicant: Micron Technology, Inc.

Inventor： Kunal R. Parekh

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H10B41/27 ,  H10B43/27

Abstract: A method of forming a microelectronic device comprises forming line structures comprising conductive material and insulative material overlying the conductive material, the line structures separated from one another by trenches. An isolation material is formed on surfaces of the line structures inside and outside of the trenches, the isolation material only partially filling the trenches to form air gaps interposed between the line structures. Openings are formed to extend through the isolation material and expose portions of the insulative material of the line structures. The exposed portions of the insulative material of the line structures are removed to form extended openings extending to the conductive material of the line structures. Conductive contact structures are formed within the extended openings. Conductive pad structures are formed on the conductive contact structures. Additional methods, microelectronic devices, memory devices, and electronic systems are also described.

公开(公告)号：US20250140753A1

公开(公告)日：2025-05-01

申请号：US18920749

申请日：2024-10-18

Applicant: Micron Technology, Inc.

Inventor： Bharat Bhushan ,  Kunal R. Parekh ,  Akshay N. Singh ,  Eiichi Nakano

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/18

Abstract: A semiconductor device assembly is disclosed. The semiconductor device assembly includes a first semiconductor die and second semiconductor dies and an additional semiconductor component coupled with the logic die. Dielectric peripheral material is disposed along sidewalls of the first die and extends beyond a first footprint of the first die. A gap fill material is disposed at the first die and at the dielectric peripheral material beyond a second footprint of the second semiconductor dies and a third footprint of the additional semiconductor component such that the gap fill material at least partially surrounds the second semiconductor dies and the additional semiconductor component.