Vertical power semiconductor carrier having laterally isolated circuit areas
    89.
    发明授权
    Vertical power semiconductor carrier having laterally isolated circuit areas 有权
    具有侧向隔离电路区域的垂直功率半导体载体

    公开(公告)号:US08502307B2

    公开(公告)日:2013-08-06

    申请号:US12953682

    申请日:2010-11-24

    IPC分类号: H01L29/66

    摘要: An integrated circuit includes a semiconductor carrier including a first side and a second side opposite the first side. An FET is in a first area of the semiconductor carrier, and has a drain electrically coupled to a drain contact area at the first side and a source electrically coupled to a source contact area at the second side. First circuit elements are in a second area of the semiconductor carrier. The second area is electrically insulated from the semiconductor carrier surrounding the second area via a trench insulation extending through the semiconductor carrier from the first side to the second side. An interconnection level electrically interconnects the first circuit elements at the second side, and is electrically insulated from the source contact area in the entire second area via an insulating layer at the second side. A conductive pathway extends through the semiconductor carrier from the first side to the second side, and is electrically insulated from the semiconductor carrier surrounding the conductive pathway. At least one of the first circuit elements is electrically coupled to a contact area at the first side via the conductive pathway.

    摘要翻译: 集成电路包括半导体载体,其包括第一侧和与第一侧相对的第二侧。 FET位于半导体载体的第一区域中,并且具有电耦合到第一侧的漏极接触区域的漏极和与第二侧的源极接触区域电耦合的源极。 第一电路元件位于半导体载体的第二区域中。 第二区域通过从第一侧延伸穿过半导体载体的沟槽绝缘体与第二区域周围的半导体载体电绝缘。 互连电平在第二侧电连接第一电路元件,并且在第二侧通过绝缘层与整个第二区域中的源极接触区域电绝缘。 导电路径从第一侧延伸穿过半导体载体到第二侧,并且与围绕导电路径的半导体载体电绝缘。 第一电路元件中的至少一个经由导电路径电耦合到第一侧的接触区域。