公开(公告)号：US10446543B2

公开(公告)日：2019-10-15

申请号：US15796816

申请日：2017-10-29

Applicant: Renesas Electronics Corporation

Inventor： Shinichi Uchida ,  Takafumi Kuramoto ,  Yasutaka Nakashiba

IPC: H01L29/06 ,  H01L27/06 ,  H01L29/94 ,  H01L21/84 ,  H01L23/522 ,  H01L23/528 ,  H01L27/12 ,  H01L29/66 ,  H01L29/93 ,  H01L23/485

Abstract: A semiconductor device of the present invention includes, in a region 1C, a top electrode made by a semiconductor layer of an SOI substrate, a capacitive insulating film made by an insulating layer, a bottom electrode made by a supporting board, and a lead part (a high-concentration impurity region of an n type) of the bottom electrode coupled to the supporting board. An SOI transistor in a region 1B is formed over a main surface of the semiconductor layer over the insulating layer as a thin film, and threshold voltage can be adjusted by applying a voltage to a well arranged on the rear face side of the insulating layer.

公开(公告)号：US10386586B2

公开(公告)日：2019-08-20

申请号：US15832795

申请日：2017-12-06

Applicant: Renesas Electronics Corporation

Inventor： Tetsuya Iida ,  Yasutaka Nakashiba

IPC: G02B6/12 ,  G02B6/42 ,  H01S5/022 ,  H01S5/042 ,  H01S5/02 ,  G02B6/30 ,  G02B6/13 ,  H01S5/024

Abstract: A Si photonics device includes: a first semiconductor chip; a second semiconductor chip having a laser diode and mounted on the first semiconductor chip; a third semiconductor chip taking in a laser beam emitted from the laser diode and mounted on the first semiconductor chip; and a resin layer disposed on the first semiconductor chip so as to face the second semiconductor chip. Further, the Si photonics device has: a bump electrode connecting the second semiconductor chip and an upper layer electrode pad provided on the resin layer of the first semiconductor chip; and a bump electrode connecting the first semiconductor chip and the third semiconductor chip, and the second semiconductor chip is mounted on the first semiconductor chip via the resin layer.

公开(公告)号：US09933568B2

公开(公告)日：2018-04-03

申请号：US15363663

申请日：2016-11-29

Applicant: Renesas Electronics Corporation

Inventor： Tohru Kawai ,  Yasutaka Nakashiba

IPC: G02B6/122 ,  H01L21/265 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L29/36 ,  G02B6/12

CPC classification number: G02B6/122 ,  G02B6/12004 ,  G02B2006/12061 ,  G02B2006/12123 ,  G02B2006/12142 ,  G02B2006/12176 ,  H01L21/26506 ,  H01L21/76898 ,  H01L23/5226 ,  H01L23/528 ,  H01L29/36

Abstract: Provided is an SOI substrate which has a substrate, an insulating layer formed over the substrate, and a semiconductor layer formed over the insulating layer. Optical waveguides are formed in the semiconductor layer of the SOI substrate. This substrate has a low resistance semiconductor layer and a high resistance semiconductor layer thereover. Further, wirings which are formed through insulating films are provided on the optical waveguides. In this manner, the low resistance semiconductor layer is arranged in the surface part of the substrate of the insulating films, thereby restraining an eddy current generated in the substrate due to an electric signal transmitted through the wirings.

公开(公告)号：US09875962B2

公开(公告)日：2018-01-23

申请号：US15456976

申请日：2017-03-13

Applicant: Renesas Electronics Corporation

Inventor： Takatsugu Nemoto ,  Yasutaka Nakashiba ,  Takasuke Hashimoto ,  Shinichi Uchida ,  Kazunori Go ,  Hiroshi Oe ,  Noriko Yoshikawa

IPC: G01R33/06 ,  H01L23/522 ,  H01F27/28 ,  H01L49/02 ,  H01L23/528 ,  G01R31/26

CPC classification number: H01L23/5227 ,  G01R15/181 ,  G01R21/00 ,  G01R31/2607 ,  G01R33/06 ,  H01F21/00 ,  H01F27/2804 ,  H01L23/5286 ,  H01L28/10

Abstract: A sensor device includes a power line and a semiconductor device. The semiconductor device includes an inductor. The inductor is formed using an interconnect layer (to be described later using FIG. 3). The power line and the semiconductor device overlap each other when viewed from a direction perpendicular to the semiconductor device. The semiconductor device includes two inductors. The power line extends between the two inductors when viewed from a direction perpendicular to the semiconductor device.

公开(公告)号：US09685496B2

公开(公告)日：2017-06-20

申请号：US14255270

申请日：2014-04-17

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasutaka Nakashiba

IPC: H01L23/34 ,  H01L49/02 ,  G01R31/28 ,  G01R31/302 ,  G01R31/303

CPC classification number: H01L28/10 ,  G01R31/2886 ,  G01R31/3025 ,  G01R31/303

Abstract: A semiconductor device includes a semiconductor chip including a main surface, an internal circuit including a plurality of transistors, formed on the main surface, a bonding pad electrically connected to the internal circuit, formed on the main surface, an inductor for communicating an external device in a non-contact manner, formed on the main surface, and a seal ring formed along an outer peripheral edge of the semiconductor chip to surround the internal circuit and the bonding pad in a plan view. The inductor has a configuration to surround the internal circuit and the bonding pad in the plan view and along the seal ring. The inductor is arranged inside the seal ring.

公开(公告)号：US09564426B2

公开(公告)日：2017-02-07

申请号：US14931991

申请日：2015-11-04

Applicant: Renesas Electronics Corporation

Inventor： Tohru Kawai ,  Yasutaka Nakashiba ,  Yutaka Akiyama

IPC: H01L27/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/739 ,  H01L29/78 ,  H01L27/07 ,  H01L23/00

CPC classification number: H01L29/7813 ,  H01L23/4952 ,  H01L23/49562 ,  H01L23/5223 ,  H01L24/05 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L27/0629 ,  H01L27/0733 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7803 ,  H01L2224/05624 ,  H01L2224/0603 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48464 ,  H01L2224/49111 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

Abstract: Performance of a semiconductor device is improved without increasing an area size of a semiconductor chip. For example, a source electrode of a power transistor and an upper electrode of a capacitor element have an overlapping portion. In other word, the upper electrode of the capacitor element is formed over the source electrode of the power transistor through a capacitor insulating film. That is, the power transistor and the capacitor element are arranged in a laminated manner in a thickness direction of the semiconductor chip. As a result, it becomes possible to add a capacitor element to be electrically coupled to the power transistor while suppressing an increase in planar size of the semiconductor chip.

Abstract translation: 提高半导体器件的性能而不增加半导体芯片的面积尺寸。 例如，功率晶体管的源电极和电容器元件的上电极具有重叠部分。 换句话说，电容器元件的上电极通过电容器绝缘膜形成在功率晶体管的源极上。 也就是说，功率晶体管和电容器元件以半导体芯片的厚度方向层叠的方式配置。 结果，可以在抑制半导体芯片的平面尺寸的增加的同时添加电耦合到功率晶体管的电容器元件。

公开(公告)号：US09529022B2

公开(公告)日：2016-12-27

申请号：US14477538

申请日：2014-09-04

Applicant: Renesas Electronics Corporation

Inventor： Takatsugu Nemoto ,  Yasutaka Nakashiba ,  Takasuke Hashimoto ,  Shinichi Uchida

IPC: G01R1/20 ,  G01R19/00 ,  G01R15/18

CPC classification number: G01R19/0092 ,  G01R1/203 ,  G01R15/181

Abstract: This invention provides a sensor device at reduced cost. The sensor device includes a printed circuit board, a first terminal, a second terminal, an interconnect line, and a semiconductor device. The first terminal and second terminal are provided on the printed circuit board and coupled to a power line. The second terminal is coupled to a downstream part of the power line with respect to the first terminal. The interconnect line is disposed on the printed circuit board to couple the first terminal and second terminal to each other. In other words, the interconnect line is coupled to the power line in parallel. The semiconductor device is mounted on the printed circuit board and includes an interconnect layer and an inductor formed in the interconnect layer.

Abstract translation: 本发明以更低的成本提供传感器装置。 传感器装置包括印刷电路板，第一端子，第二端子，互连线和半导体器件。 第一端子和第二端子设置在印刷电路板上并耦合到电力线。 第二端子相对于第一端子耦合到电力线的下游部分。 互连线布置在印刷电路板上以将第一端子和第二端子彼此耦合。 换句话说，互连线并联耦合到电力线。 半导体器件安装在印刷电路板上，并且包括形成在互连层中的互连层和电感器。

公开(公告)号：US09508662B2

公开(公告)日：2016-11-29

申请号：US14827841

申请日：2015-08-17

Applicant: Renesas Electronics Corporation

Inventor： Hiroyuki Kunishima ,  Yasutaka Nakashiba ,  Masaru Wakabayashi ,  Shinichi Watanuki ,  Ken Ozawa ,  Tatsuya Usami ,  Yoshiaki Yamamoto ,  Keiji Sakamoto

IPC: G02B6/12 ,  H01L23/60 ,  G02F1/01 ,  G02F1/025 ,  H01L31/02 ,  H05K1/02 ,  G02B6/43

CPC classification number: H01L23/60 ,  G02B6/43 ,  G02F1/0121 ,  G02F1/025 ,  G02F2201/12 ,  G02F2202/105 ,  H01L31/02002 ,  H01L2924/0002 ,  H05K1/0296 ,  H01L2924/00

Abstract: A technique is provided which can prevent the quality of an electrical signal from degrading in an optical semiconductor device.In a cross-section perpendicular to an extending direction of an electrical signal transmission line, the electrical signal transmission line is surrounded by a shielding portion including a first noise cut wiring, second plugs, a first layer wiring, first plugs, a shielding semiconductor layer, first plugs, a first layer wiring, second plugs, and a second noise cut wiring, and the shielding portion is fixed to a reference potential. Thereby, the shielding portion blocks noise due to effects of a magnetic field or an electric field from the semiconductor substrate, which affects the electrical signal transmission line.

Abstract translation: 在垂直于电信号传输线的延伸方向的横截面中，电信号传输线由屏蔽部分包围，该屏蔽部分包括第一噪声切断布线，第二插塞，第一层布线，第一插塞，屏蔽半导体层 ，第一插头，第一层布线，第二插头和第二噪声切断布线，并且屏蔽部分被固定为参考电位。 因此，屏蔽部分由于影响电信号传输线的来自半导体衬底的磁场或电场的影响而阻塞噪声。

公开(公告)号：US09496203B2

公开(公告)日：2016-11-15

申请号：US14727446

申请日：2015-06-01

Applicant: Renesas Electronics Corporation

Inventor： Akira Matsumoto ,  Yoshinao Miura ,  Yasutaka Nakashiba

IPC: H01L23/482 ,  H01L27/088 ,  H01L27/02 ,  H01L29/417 ,  H01L23/50 ,  H01L23/492 ,  H01L23/528 ,  H01L23/00 ,  H01L27/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/778 ,  H01L23/495 ,  H01L29/10 ,  H01L29/20

CPC classification number: H01L23/49562 ,  H01L23/4824 ,  H01L23/485 ,  H01L23/492 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49548 ,  H01L23/49575 ,  H01L23/50 ,  H01L23/528 ,  H01L23/5283 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L27/0203 ,  H01L27/0605 ,  H01L27/088 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/41758 ,  H01L29/4236 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/78 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/45014 ,  H01L2224/451 ,  H01L2224/4805 ,  H01L2224/4813 ,  H01L2224/48177 ,  H01L2224/48247 ,  H01L2224/49113 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/1033 ,  H01L2924/10344 ,  H01L2924/13064 ,  H01L2924/30101 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: Disclosed is a semiconductor device in which a resistance component resulting from wiring is reduced. A plurality of transistor units are arranged side by side in a first direction (Y direction in the view), each of which has a plurality of transistors. The gate electrodes of the transistors extend in the first direction. First source wiring extends between first transistor unit and second transistor unit, and first drain wiring extends between the second transistor unit and third transistor unit. Second drain wiring extends on the side of the first transistor unit opposite to the side where the first source wiring extends, and second source wiring extends on the side of the third transistor unit opposite to the side where the second drain wiring extends.

公开(公告)号：US20160056115A1

公开(公告)日：2016-02-25

申请号：US14827841

申请日：2015-08-17

Applicant: Renesas Electronics Corporation

Inventor： Hiroyuki Kunishima ,  Yasutaka Nakashiba ,  Masaru Wakabayashi ,  Shinichi Watanuki ,  Ken Ozawa ,  Tatsuya Usami ,  Yoshiaki Yamamoto ,  Keiji Sakamoto

IPC: H01L23/60 ,  H05K1/02

CPC classification number: H01L23/60 ,  G02B6/43 ,  G02F1/0121 ,  G02F1/025 ,  G02F2201/12 ,  G02F2202/105 ,  H01L31/02002 ,  H01L2924/0002 ,  H05K1/0296 ,  H01L2924/00

Abstract: A technique is provided which can prevent the quality of an electrical signal from degrading in an optical semiconductor device.In a cross-section perpendicular to an extending direction of an electrical signal transmission line, the electrical signal transmission line is surrounded by a shielding portion including a first noise cut wiring, second plugs, a first layer wiring, first plugs, a shielding semiconductor layer, first plugs, a first layer wiring, second plugs, and a second noise cut wiring, and the shielding portion is fixed to a reference potential. Thereby, the shielding portion blocks noise due to effects of a magnetic field or an electric field from the semiconductor substrate, which affects the electrical signal transmission line.

Abstract translation: 提供了可以防止电信号在光半导体器件中劣化的技术。 在垂直于电信号传输线的延伸方向的横截面中，电信号传输线由屏蔽部分包围，该屏蔽部分包括第一噪声切断布线，第二插塞，第一层布线，第一插塞，屏蔽半导体层 ，第一插头，第一层布线，第二插头和第二噪声切断布线，并且屏蔽部分被固定为参考电位。 因此，屏蔽部分由于影响电信号传输线的来自半导体衬底的磁场或电场的影响而阻塞噪声。