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81.发明授权公开(公告)号：US10135647B2
公开(公告)日：2018-11-20
申请号：US15878149
申请日：2018-01-23
Applicant: Rambus Inc.
Inventor： Jared L. Zerbe , Fariborz Assaderaghi , Brian S. Leibowitz , Hae-Chang Lee , Jihong Ren , Qi Lin
IPC: H04L25/03
Abstract: A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.
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82.发明申请公开(公告)号：US20180262323A1
公开(公告)日：2018-09-13
申请号：US15913764
申请日：2018-03-06
Applicant: Rambus Inc.
Inventor： Hae-Chang Lee , Jared L. Zerbe , Carl William Werner
CPC classification number: H04L7/0278 , H03L7/0814 , H03L7/0816 , H03L7/0818 , H03L7/091 , H03L2207/50 , H04L7/0008 , H04L7/0016 , H04L7/0079 , H04L7/0087 , H04L7/033 , H04L7/0337 , H04L7/0338
Abstract: A circuit for performing clock recovery according to a received digital signal. The circuit includes at least an edge sampler and a data sampler for sampling the digital signal, and a clock signal supply circuit. The clock signal supply circuit provides edge clock and data clock signals offset in phase from one another to the respective clock inputs of the edge sampler and the data sampler. A digital phase detector determines if the data clock is early, late or synchronized with respect to data value transitions in the digital signal, and based on that determination provides a phase adjustment signal to the clock signal supply circuit, which is operable to vary phases of the data and edge clock signals accordingly.
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公开(公告)号：US10003484B2
公开(公告)日：2018-06-19
申请号：US15652059
申请日：2017-07-17
Applicant: Rambus Inc.
Inventor： Jared L. Zerbe , Fred F. Chen , Andrew Ho , Ramin Farjad-Rad , John W. Poulton , Kevin S. Donnelly , Brian S. Leibowitz
IPC: H04L27/01 , H04L7/033 , H04L1/00 , H04L25/03 , H04W52/20 , H04L25/497 , H04L25/02 , H04W52/22 , H04L7/00
CPC classification number: H04L27/01 , H04L1/0026 , H04L7/0025 , H04L7/0087 , H04L7/0337 , H04L25/0272 , H04L25/028 , H04L25/03057 , H04L25/03343 , H04L25/03885 , H04L25/497 , H04L2025/03503 , H04W52/20 , H04W52/225 , Y02D70/00
Abstract: A signaling system includes a pre-emphasizing transmitter and an equalizing receiver coupled to one another via a high-speed signal path. The receiver measures the quality of data conveyed from the transmitter. A controller uses this information and other information to adaptively establish appropriate transmit pre-emphasis and receive equalization settings, e.g. to select the lowest power setting for which the signaling system provides some minimum communication bandwidth without exceeding a desired bit-error rate.
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公开(公告)号：US09973177B1
公开(公告)日：2018-05-15
申请号：US15360149
申请日：2016-11-23
Applicant: Rambus Inc.
Inventor： Yue Lu , Jared L. Zerbe
CPC classification number: H03K5/00006 , H03J2200/10 , H03L7/0802 , H03L7/083 , H03L7/085 , H03L7/099 , H03L7/0995 , H03L7/16 , H03L7/24 , H04L7/033
Abstract: In a clock generating circuit having a plurality of injection-locking oscillators, a first one of the injection-locking oscillators is enabled to output a free-running reference clock signal and a control value is generated based at least in part on a frequency relationship between the free-running reference clock signal and an input timing signal. In accordance with the control value, a selected one of the injection-locking oscillators is enabled to generate an output clock signal that is frequency-locked with respect to the input timing signal.
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公开(公告)号：US20170169877A1
公开(公告)日：2017-06-15
申请号：US15389407
申请日：2016-12-22
Applicant: Rambus Inc.
Inventor： Jared L. Zerbe , Frederick A. Ware
IPC: G11C11/4076
CPC classification number: G11C11/4076 , G06F1/04 , G06F13/4243 , G11C7/04 , G11C7/1078 , G11C7/1093 , G11C7/22 , G11C7/222 , G11C29/022 , G11C29/023 , G11C29/028 , G11C2207/2254 , H04L7/0008 , Y02D10/14 , Y02D10/151
Abstract: A method of operating a memory controller is disclosed. The method includes transmitting data signals to a memory device over each one of at least two parallel data links. A timing signal is sent to the memory device on a first dedicated link. The timing signal has a fixed phase relationship with the data signals. A data strobe signal is driven to the memory device on a second dedicated link. Phase information is received from the memory device. The phase information being generated internal to the memory device and based on a comparison between the timing signal and a version of the data strobe signal internally distributed within the memory device. A phase of the data strobe signal is adjusted relative to the timing signal based on the received phase information.
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Patent Agency Ranking
86.发明申请METHODS AND CIRCUITS FOR ASYMMETRIC DISTRIBUTION OF CHANNEL EQUALIZATION BETWEEN DEVICES 有权用于设备之间的通道均衡化的不对称分配的方法和电路公开(公告)号：US20170054577A1
公开(公告)日：2017-02-23
申请号：US15233557
申请日：2016-08-10
Applicant: Rambus Inc.
Inventor： Jared L. Zerbe , Fariborz Assaderaghi , Brian S. Leibowitz , Hae-Chang Lee , Jihong Ren , Qi Lin
IPC: H04L25/03
CPC classification number: H04L25/03343 , H04L25/03057 , H04L25/0307 , H04L25/03885 , H04L2025/03356 , H04L2025/03433 , H04L2025/03617
Abstract: A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.
Abstract translation: 收发器架构支持在高性能集成电路（IC）和使用较不复杂的发送器和接收器的一个或多个相对低性能的IC之间延伸的信号通道上的高速通信。 该架构通过在车道的较高性能侧实例化相对复杂的发送和接收均衡电路来补偿通过双向通道通信的IC之间的性能不对称性。 基于在高性能IC的接收机处的信号响应，可以自适应地更新高性能IC中的发送和接收均衡滤波器系数。
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公开(公告)号：US09536589B2
公开(公告)日：2017-01-03
申请号：US14445014
申请日：2014-07-28
Applicant: Rambus Inc.
Inventor： Jared L. Zerbe , Frederick A. Ware
CPC classification number: G11C11/4076 , G06F1/04 , G06F13/4243 , G11C7/04 , G11C7/1078 , G11C7/1093 , G11C7/22 , G11C7/222 , G11C29/022 , G11C29/023 , G11C29/028 , G11C2207/2254 , H04L7/0008 , Y02D10/14 , Y02D10/151
Abstract: A method of operating a memory controller is disclosed. The method includes transmitting data signals to a memory device over each one of at least two parallel data links. A timing signal is sent to the memory device on a first dedicated link. The timing signal has a fixed phase relationship with the data signals. A data strobe signal is driven to the memory device on a second dedicated link. Phase information is received from the memory device. The phase information being generated internal to the memory device and based on a comparison between the timing signal and a version of the data strobe signal internally distributed within the memory device. A phase of the data strobe signal is adjusted relative to the timing signal based on the received phase information.
Abstract translation: 公开了一种操作存储器控制器的方法。 该方法包括通过至少两个并行数据链路中的每一个将数据信号发送到存储器设备。 在第一专用链路上将定时信号发送到存储设备。 定时信号与数据信号具有固定的相位关系。 数据选通信号被驱动到第二专用链路上的存储器件。 从存储器件接收相位信息。 所述相位信息在存储器件内部产生，并且基于定时信号与内部分布在存储器件内的数据选通信号的版本之间的比较。 基于接收的相位信息，相对于定时信号调整数据选通信号的相位。
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公开(公告)号：US09531391B1
公开(公告)日：2016-12-27
申请号：US14715537
申请日：2015-05-18
Applicant: Rambus Inc.
Inventor： Yue Lu , Jared L. Zerbe
CPC classification number: H03K5/00006 , H03J2200/10 , H03L7/0802 , H03L7/083 , H03L7/085 , H03L7/099 , H03L7/0995 , H03L7/16 , H03L7/24 , H04L7/033
Abstract: Upon detecting transition of an input timing signal from a non-oscillating state to an oscillating state, a clock generating circuit is switched from a paused mode to an open-loop operating mode to transition an output timing signal of the clock generating circuit from a non-oscillating state to an oscillating state in which the output timing signal oscillates at a free-running frequency. A ratio of a reference frequency of the oscillating-state input timing signal and the free-running frequency of the output timing signal is determined and used to adjust a frequency-lock range of the clock generating circuit. The clock generating circuit is then switched from the open-loop operating state to the closed-loop operating state to frequency-lock the output timing signal with respect to the reference frequency of the input timing signal.
Abstract translation: 当检测到输入定时信号从非振荡状态向振荡状态的转变时，时钟发生电路从暂停模式切换到开环工作模式，以将时钟产生电路的输出定时信号从非 振荡状态到输出定时信号以自由运行频率振荡的振荡状态。 确定振荡状态输入定时信号的参考频率与输出定时信号的自由运行频率的比率，并用于调整时钟发生电路的频率锁定范围。 然后，时钟产生电路从开环工作状态切换到闭环工作状态，以相对于输入定时信号的参考频率对输出定时信号进行频率锁定。
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公开(公告)号：US09397868B1
公开(公告)日：2016-07-19
申请号：US14050223
申请日：2013-10-09
Applicant: Rambus Inc.
Inventor： Masum Hossain , Jared L. Zerbe
CPC classification number: H04L25/03057 , H03L7/00 , H04L7/0087 , H04L7/033
Abstract: This disclosure provides a split-path equalizer and a clock recovery circuit. More particularly, clock recovery operation is enhanced, particularly at high-signaling rates, by separately equalizing each of a data path and an edge path. In specific embodiments, the data path is equalized in a manner that maximizes signal-to-noise ratio and the edge path is equalized in a manner that emphasizes symmetric edge response for a single unit interval and zero edge response for other unit intervals (e.g., irrespective of peak voltage margin). Such equalization tightens edge grouping and thus enhances clock recovery, while at the same time optimizing data-path sampling. Techniques are also disclosed for addressing split-path equalization-induced skew.
Abstract translation: 本公开提供了分路通均衡器和时钟恢复电路。 更具体地，通过分别均衡数据路径和边缘路径中的每一个，特别是在高信令速率下，时钟恢复操作被增强。 在具体实施例中，以使信噪比最大化的方式均衡数据路径，并且以强调单个单位间隔的对称边缘响应并且对于其它单位间隔为零边缘响应的方式均衡边缘路径（例如， 不考虑峰值电压裕度）。 这种均衡使边缘分组变紧，从而增强时钟恢复，同时优化数据路径采样。 还公开了用于寻址分路均衡引起的偏移的技术。
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公开(公告)号：US09344064B2
公开(公告)日：2016-05-17
申请号：US14808936
申请日：2015-07-24
Applicant: Rambus Inc.
Inventor： Kambiz Kaviani , Kashinath Prabhu , Brian Hing-Kit Tsang , Jared L. Zerbe
Abstract: Embodiments of an integrated circuit (IC) comprising frequency change detection circuitry are described. Some embodiments include first circuitry to generate a second clock signal based on a first clock signal, wherein the first clock signal has a first clock frequency, and wherein the second clock signal has a second clock frequency that is an integral multiple of the first clock frequency. The embodiments further include second circuitry to obtain samples by oversampling the first clock signal using the second clock signal. Additionally, the embodiments include third circuitry to detect a change in the first clock frequency based on the samples.
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