公开(公告)号：US20140327152A1

公开(公告)日：2014-11-06

申请号：US14337011

申请日：2014-07-21

申请人： XINTEC INC.

发明人： Tsang-Yu LIU ,  Chia-Ming CHENG

IPC分类号： H01L23/48

CPC分类号： H01L23/481 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/585 ,  H01L24/11 ,  H01L24/13 ,  H01L27/14618 ,  H01L2224/02311 ,  H01L2224/02371 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/11002 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/93 ,  H01L2924/10158 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/16235 ,  H01L2224/11 ,  H01L2924/014 ,  H01L2924/00

摘要： A chip package includes: a substrate having a first surface, a second surface, and a side surface connecting the first and the second surfaces; a dielectric layer located on the first surface; conducting pads comprising a first and a second conducting pads located in the dielectric layer; openings extending from the second surface towards the first surface and correspondingly exposing the conducting pads, wherein a first opening of the openings and a second opening of the openings next to the first opening respectively expose the first and the second conducting pads and extend along a direction intersecting the side surface of the substrate to respectively extend beyond the first and the second conducting pads; and a first and a second wire layers located on the second surface and extending into the first the second openings to electrically contact with the first and the second conducting pads, respectively.

摘要翻译： 芯片封装包括：具有第一表面，第二表面和连接第一和第二表面的侧表面的基板; 位于所述第一表面上的电介质层; 导电焊盘，包括位于介电层中的第一和第二导电焊盘; 开口从第二表面延伸到第一表面并相应地暴露导电垫，其中开口的第一开口和与第一开口相邻的开口的第二开口分别露出第一和第二导电垫并沿着方向 与衬底的侧表面相交，分别延伸超过第一和第二导电焊盘; 以及位于第二表面上并分别延伸到第一个第二开口中以分别与第一和第二导电垫电接触的第一和第二导线层。

公开(公告)号：US20140312482A1

公开(公告)日：2014-10-23

申请号：US14255872

申请日：2014-04-17

申请人： XINTEC INC.

发明人： Chun-Wei CHANG ,  Kuei-Wei CHEN ,  Chia-Ming CHENG ,  Chia-Sheng LIN ,  Chien-Hui CHEN ,  Tsang-Yu LIU

IPC分类号： H01L23/00

CPC分类号： H01L24/26 ,  H01L21/6835 ,  H01L21/76898 ,  H01L21/78 ,  H01L21/784 ,  H01L23/3192 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/27 ,  H01L24/94 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05009 ,  H01L2224/05548 ,  H01L2224/05562 ,  H01L2224/05566 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/11002 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/94 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/00 ,  H01L2224/11 ,  H01L2924/014 ,  H01L2224/03

摘要： A wafer level array of chips is provided. The wafer level array of chips comprises a semiconductor wafer, and a least one extending-line protection. The semiconductor wafer has at least two chips, which are arranged adjacent to each other, and a carrier layer. Each chip has an upper surface and a lower surface, and comprises at least one device. The device is disposed upon the upper surface, covered by the carrier layer. The extending-line protection is disposed under the carrier layer and between those two chips. The thickness of the extending-line protection is less than that of the chip. Wherein the extending-line protection has at least one extending-line therein. In addition, a chip package fabricated by the wafer level array of chips, and a method thereof are also provided.

摘要翻译： 提供晶片级的芯片阵列。 晶片级的芯片阵列包括半导体晶片和至少一个延伸线保护。 半导体晶片具有彼此相邻布置的至少两个芯片和载体层。 每个芯片具有上表面和下表面，并且包括至少一个装置。 该装置设置在上表面上，被载体层覆盖。 延伸线保护设置在载体层之下和两个芯片之间。 延长线保护的厚度小于芯片的厚度。 其中延伸线保护件中至少有一条延伸线。 此外，还提供了由晶片级阵列芯片制造的芯片封装及其方法。

公开(公告)号：US20140199830A1

公开(公告)日：2014-07-17

申请号：US14214408

申请日：2014-03-14

申请人： XINTEC INC.

发明人： Yu-Lin YEN ,  Chien-Hui CHEN ,  Tsang-Yu LIU ,  Long-Sheng YEOU

IPC分类号： H01L21/768

CPC分类号： H01L21/76879 ,  B81B7/007 ,  B81B2207/07 ,  B81B2207/092 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/06 ,  H01L24/32 ,  H01L24/94 ,  H01L2221/68377 ,  H01L2224/0557 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01021 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2924/00 ,  H01L2224/05552

摘要： According to an embodiment of the invention, a chip package is provided. The chip package includes: a substrate having an upper surface and a lower surface; a plurality of conducting pads located under the lower surface of the substrate; a dielectric layer located between the conducting pads; a trench extending from the upper surface towards the lower surface of the substrate; a hole extending from a bottom of the trench towards the lower surface of the substrate, wherein a sidewall of the hole is substantially perpendicular to the lower surface of the substrate, and the sidewall or a bottom of the hole exposes a portion of the conducting pads; and a conducting layer located in the hole and electrically connected to at least one of the conducting pads.

摘要翻译： 根据本发明的实施例，提供了芯片封装。 芯片封装包括：具有上表面和下表面的基板; 位于所述基板的下表面下方的多个导电垫; 位于导电垫之间的电介质层; 从衬底的上表面延伸到下表面的沟槽; 从所述沟槽的底部延伸到所述衬底的下表面的孔，其中所述孔的侧壁基本上垂直于所述衬底的下表面，并且所述孔的侧壁或所述底部露出所述导电垫的一部分 ; 以及导电层，其位于所述孔中并电连接到至少一个所述导电焊盘。

公开(公告)号：US20140084458A1

公开(公告)日：2014-03-27

申请号：US14036954

申请日：2013-09-25

申请人： XINTEC INC.

发明人： Yu-Ting HUANG ,  Tsang-Yu LIU

IPC分类号： H01L23/498 ,  H01L21/768

CPC分类号： H01L23/49827 ,  B81B7/0061 ,  H01L21/76885 ,  H01L23/3107 ,  H01L23/481 ,  H01L2224/13 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/00

摘要： An embodiment of the invention provides a chip package which includes: a substrate having a first surface and a second surface; a sensing layer disposed on the first surface of the substrate, wherein the sensing layer has a sensing region; a conducting pad structure disposed on the substrate and electrically connected to the sensing region; a spacer layer disposed on the first surface of the substrate; a semiconductor substrate placed on the spacer layer, wherein the semiconductor substrate, the spacer layer, and the substrate together surround a cavity on the sensing region; and a through-hole extending from a surface of the semiconductor substrate toward the substrate, wherein the through-hole connects to the cavity.

摘要翻译： 本发明的实施例提供了一种芯片封装，其包括：具有第一表面和第二表面的基板; 感测层，其设置在所述基板的所述第一表面上，其中所述感测层具有感测区域; 导电焊盘结构，设置在所述基板上并电连接到所述感测区域; 设置在所述基板的第一表面上的间隔层; 放置在间隔层上的半导体衬底，其中半导体衬底，间隔层和衬底一起围绕感测区域上的空腔; 以及从半导体衬底的表面朝向衬底延伸的通孔，其中所述通孔连接到所述腔。

公开(公告)号：US20140065769A1

公开(公告)日：2014-03-06

申请号：US14074519

申请日：2013-11-07

申请人： XINTEC INC.

发明人： Yu-Lung HUANG ,  Tsang-Yu LIU

IPC分类号： H01L23/00

CPC分类号： H01L24/94 ,  H01L23/3114 ,  H01L23/3171 ,  H01L27/14618 ,  H01L27/14627 ,  H01L31/048 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15788 ,  H04N5/2257 ,  H01L2924/00

摘要： An embodiment of the invention provides a chip package, which includes: a semiconductor substrate having a device region; a package layer disposed on the semiconductor substrate; a spacing layer disposed between the semiconductor substrate and the package layer and surrounding the device region; and an auxiliary pattern having a hollow pattern formed in the spacing layer, a material pattern located between the spacing layer and the device region, or combinations thereof.

摘要翻译： 本发明的实施例提供一种芯片封装，其包括：具有器件区域的半导体衬底; 封装层，设置在所述半导体衬底上; 间隔层，设置在所述半导体衬底和所述封装层之间并且围绕所述器件区域; 以及形成在间隔层中的中空图案的辅助图案，位于间隔层和器件区域之间的材料图案，或其组合。

公开(公告)号：US20130307137A1

公开(公告)日：2013-11-21

申请号：US13898300

申请日：2013-05-20

申请人： XINTEC INC.

发明人： Po-Shen LIN ,  Tsang-Yu LIU ,  Yen-Shih HO ,  Chih-Wei HO ,  Yu-Min LIANG

IPC分类号： H01L23/498 ,  H01L21/78

CPC分类号： H01L23/498 ,  B81B7/0077 ,  H01L21/78 ,  H01L24/94 ,  H01L27/14618 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/00

摘要： Embodiments of the present invention provide a chip package including: a semiconductor substrate having a first surface and a second surface; a device region formed in the semiconductor substrate; a dielectric layer disposed on the first surface; and a conducting pad structure disposed in the dielectric layer and electrically connected to the device region; a cover substrate disposed between the chip and the cover substrate, wherein the spacer layer, a cavity is created an surrounded by the chip and the cover substrate on the device region, and the spacer layer is in direct contact with the chip without any adhesion glue disposed between the chip and the spacer layer.

摘要翻译： 本发明的实施例提供了一种芯片封装，包括：具有第一表面和第二表面的半导体衬底; 形成在所述半导体衬底中的器件区域; 设置在所述第一表面上的电介质层; 以及导电焊盘结构，其设置在所述电介质层中并电连接到所述器件区域; 设置在所述芯片和所述盖基板之间的覆盖基板，其中所述间隔层，空腔由所述芯片和所述器件区域上的覆盖基板所围绕，并且所述间隔层与所述芯片直接接触而没有任何粘合胶 设置在芯片和间隔层之间。

公开(公告)号：US20130196470A1

公开(公告)日：2013-08-01

申请号：US13802262

申请日：2013-03-13

申请人： XINTEC INC.

发明人： Chia-Lun TSAI ,  Tsang-Yu LIU ,  Chia-Ming CHENG

IPC分类号： H01L21/78

CPC分类号： H01L21/78 ,  H01L21/76898 ,  H01L23/552 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/29 ,  H01L24/32 ,  H01L24/92 ,  H01L24/94 ,  H01L2224/023 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/2919 ,  H01L2224/73253 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01029 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2224/83 ,  H01L2924/0665 ,  H01L2924/00 ,  H01L2224/05552

摘要： A chip package includes a substrate having a pad region, a device region, and a remained scribe region located at a periphery of the substrate; a signal and an EMI ground pads disposed on the pad region; a first and a second openings penetrating into the substrate to expose the signal and the EMI ground pads, respectively; a first and a second conducting layers located in the first and the second openings and electrically connecting the signal and the EMI ground pads, respectively, wherein the first conducting layer and the signal pad are separated from a periphery of the remained scribe region, and wherein a portion of the second conducting layer and/or the EMI ground pad extend(s) to a periphery of the remained scribe region; and a third conducting layer surrounding the periphery of the remained scribe region to electrically connect the second conducting layer and/or the EMI ground pad.

摘要翻译： 芯片封装包括具有焊盘区域，器件区域和位于衬底周围的残留刻划区域的衬底; 设置在所述焊盘区域上的信号和EMI接地焊盘; 分别穿入基板以暴露信号和EMI接地焊盘的第一和第二开口; 位于所述第一和第二开口中的第一和第二导电层，分别电连接所述信号和所述EMI接地焊盘，其中所述第一导电层和所述信号焊盘与所述残留划线区域的外围分离，并且其中 所述第二导电层和/或所述EMI接地垫的一部分延伸到所述残留划线区域的周边; 以及围绕剩余划线区域的周边的第三导电层，以电连接第二导电层和/或EMI接地垫。

公开(公告)号：US20130119556A1

公开(公告)日：2013-05-16

申请号：US13678507

申请日：2012-11-15

申请人： Xintec Inc.

发明人： Tsang-Yu LIU ,  Chia-Ming CHENG

IPC分类号： H01L23/48

CPC分类号： H01L23/481 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/585 ,  H01L24/11 ,  H01L24/13 ,  H01L27/14618 ,  H01L2224/02311 ,  H01L2224/02371 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/11002 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/93 ,  H01L2924/10158 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/16235 ,  H01L2224/11 ,  H01L2924/014 ,  H01L2924/00

摘要： A chip package includes: a substrate having a first surface, a second surface, and a side surface connecting the first and the second surfaces; a dielectric layer located on the first surface; conducting pads comprising a first and a second conducting pads located in the dielectric layer; openings extending from the second surface towards the first surface and correspondingly exposing the conducting pads, wherein a first opening of the openings and a second opening of the openings next to the first opening respectively expose the first and the second conducting pads and extend along a direction intersecting the side surface of the substrate to respectively extend beyond the first and the second conducting pads; and a first and a second wire layers located on the second surface and extending into the first the second openings to electrically contact with the first and the second conducting pads, respectively.

摘要翻译： 芯片封装包括：具有第一表面，第二表面和连接第一和第二表面的侧表面的基板; 位于所述第一表面上的电介质层; 导电焊盘，包括位于介电层中的第一和第二导电焊盘; 开口从第二表面延伸到第一表面并相应地暴露导电垫，其中开口的第一开口和与第一开口相邻的开口的第二开口分别露出第一和第二导电垫，并沿着方向 与衬底的侧表面相交，分别延伸超过第一和第二导电焊盘; 以及位于第二表面上并分别延伸到第一个第二开口中以分别与第一和第二导电垫电接触的第一和第二导线层。