公开(公告)号：US09401342B2

公开(公告)日：2016-07-26

申请号：US13929688

申请日：2013-06-27

Applicant: Shun Meen Kuo ,  Margaret Szymanowski ,  Paul Hart

Inventor： Shun Meen Kuo ,  Margaret Szymanowski ,  Paul Hart

IPC: H03F3/68 ,  H03F3/195 ,  H01L23/00 ,  H03F1/02 ,  H03F1/56 ,  H03F3/24 ,  H01L23/047 ,  H01L23/552 ,  H01L23/66 ,  H01L23/24

CPC classification number: H01L24/85 ,  H01L23/047 ,  H01L23/24 ,  H01L23/552 ,  H01L23/66 ,  H01L24/45 ,  H01L24/49 ,  H01L2223/6611 ,  H01L2223/6644 ,  H01L2223/6655 ,  H01L2223/6661 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/49175 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/19107 ,  H01L2924/3011 ,  H01L2924/30111 ,  H03F1/0288 ,  H03F1/56 ,  H03F3/195 ,  H03F3/245 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A system and method for a package including a wire bond wall to reduce coupling is presented. The package includes a substrate, and a first circuit on the substrate. The first circuit includes a first electrical device, a second electrical device, and a first wire bond array interconnecting the first electrical device and the second electrical device. The package includes a second circuit on the substrate adjacent to the first circuit, the second circuit includes a second wire bond array interconnecting a third electrical device and a fourth electrical device. The package includes a wire bond wall including a plurality of wire bonds over the substrate between the first circuit and the second circuit. The wire bond wall is configured to reduce an electromagnetic coupling between the first circuit and the second circuit during an operation of at least one of the first circuit and the second circuit.

Abstract translation: 提出了一种用于包装件的系统和方法，其包括用于减少耦合的线接合壁。 所述封装包括衬底和所述衬底上的第一电路。 第一电路包括第一电气设备，第二电气设备和互连第一电气设备和第二电气设备的第一引线键合阵列。 所述封装包括与所述第一电路相邻的所述衬底上的第二电路，所述第二电路包括互连第三电气设备和第四电气设备的第二引线接合阵列。 该封装包括引线接合壁，其包括在第一电路和第二电路之间的衬底上的多个引线键合。 引线接合壁被配置为在第一电路和第二电路中的至少一个的操作期间减小第一电路和第二电路之间的电磁耦合。

公开(公告)号：US09401338B2

公开(公告)日：2016-07-26

申请号：US13688820

申请日：2012-11-29

Applicant: Alan J. Magnus ,  Francisco Chaidez

Inventor： Alan J. Magnus ,  Francisco Chaidez

IPC: H01L23/48 ,  H01L23/00 ,  H01L25/065 ,  H01L25/03 ,  H01L25/00 ,  H01L21/56 ,  H01L23/538 ,  H01L25/18

CPC classification number: H01L24/19 ,  H01L21/561 ,  H01L21/568 ,  H01L23/5389 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L24/96 ,  H01L25/03 ,  H01L25/0652 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/05554 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48247 ,  H01L2224/48464 ,  H01L2224/48482 ,  H01L2224/49175 ,  H01L2224/73227 ,  H01L2224/73265 ,  H01L2224/85051 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18165 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: An embodiment of an electronic device includes an IC die with a top surface and a bond pad exposed at the top surface. A stud bump (or stack of stud bumps) is connected to the bond pad, and the stud bump and die are encapsulated with encapsulant. A trench is formed from a top surface of the encapsulant to the stud bump, resulting in the formation of a trench-oriented surface of the stud bump, which is exposed at the bottom of the trench. An end of an interconnect is connected to the trench-oriented surface of the stud bump. The interconnect extends above the encapsulant top surface, and may be coupled to another IC die of the same electronic device, another IC die that is distinct from the device, or another conductive feature of the device or a larger electronic system in which the device is incorporated.

Abstract translation: 电子设备的一个实施例包括具有顶表面的IC芯片和在顶表面处暴露的接合焊盘。 螺栓凸块（或螺柱凸起的堆叠）连接到接合焊盘，并且螺柱凸块和管芯用密封剂封装。 沟槽由密封剂的顶表面形成到凸起凸起部，从而形成凸起凸起的沟槽取向表面，其暴露在沟槽的底部。 互连的一端连接到螺柱凸起的沟槽取向表面。 互连延伸在密封剂顶表面上方，并且可以耦合到同一电子器件的另一个IC管芯，与该器件不同的另一个IC管芯，或该器件的另一个导电特征或该器件的较大电子系统 并入。

公开(公告)号：US09400861B2

公开(公告)日：2016-07-26

申请号：US14324392

申请日：2014-07-07

Applicant: John Avis Shepherd ,  Kamel Abouda ,  Bertrand Vrignon

Inventor： John Avis Shepherd ,  Kamel Abouda ,  Bertrand Vrignon

IPC: G06F17/50 ,  H04B15/04

CPC classification number: G06F17/5068 ,  G06F17/5009 ,  G06F17/5036 ,  G06F17/504 ,  G06F17/505 ,  H04B15/04 ,  Y02T10/82

Abstract: There is described a method of optimizing the design of an electronic device with respect to electromagnetic emissions based on frequency spreading. With the method, a designer can, for example, perform a transient simulation on the device only once, and then add frequency spreading with specific parameters by simulation. The resulting frequency spread signal can be observed. The designer can thus evaluate the reduction in electromagnetic emission level, and repeat this process by iteratively applying frequency spreading each time with specific parameters but without having to modify the schematic of the device and to perform another simulation of the device. The method according to this innovation is extremely rapid as the simulation of the design does not need to be repeated at each run of the frequency spreading simulation.

Abstract translation: 描述了基于频率扩展优化电子设备相对于电磁发射的设计的方法。 使用该方法，设计者可以例如在器件上执行一次瞬态仿真，然后通过仿真添加具有特定参数的频率扩展。 可以观察所得到的频率扩展信号。 因此，设计者可以评估电磁辐射水平的降低，并且通过每次用特定参数迭代地施加频率扩展而不必修改设备的原理图并执行设备的另一个仿真来重复该过程。 根据这一创新的方法非常快，因为在频率扩展模拟的每次运行时不需要重复设计的仿真。

公开(公告)号：US09400711B2

公开(公告)日：2016-07-26

申请号：US14251719

申请日：2014-04-14

Applicant: Ravindraraj Ramaraju ,  Mihir A. Pandya ,  Andrew C. Russell

Inventor： Ravindraraj Ramaraju ,  Mihir A. Pandya ,  Andrew C. Russell

IPC: G11C29/00 ,  G06F11/10

CPC classification number: G06F11/1064

Abstract: A content addressable memory (CAM) includes a first entry which includes one or more bits, a second entry which includes one or more bits, first comparison circuitry configured to compare each bit of a comparand to a corresponding bit of the one or more bits of the first entry and to provide a hit/miss indicator in response thereto, and second comparison circuitry configured to compare each bit of the one or more bits of the first entry to a corresponding bit of the one or more bits of the second entry and to provide a fault indicator in response thereto.

Abstract translation: 内容可寻址存储器（CAM）包括包括一个或多个比特的第一条目，包括一个或多个比特的第二条目，第一比较电路，被配置为将对比的每个比特与一个或多个比特的相应比特进行比较 第一条目并响应于此提供命中/未命中指示符，以及第二比较电路，其被配置为将第一条目的一个或多个比特的每个比特与第二条目的一个或多个比特的对应比特进行比较， 提供响应于此的故障指示器。

公开(公告)号：US09392640B2

公开(公告)日：2016-07-12

申请号：US13632549

申请日：2012-10-01

Applicant: Freescale Semiconductor, Inc.

Inventor： Tuongvu V. Nguyen ,  John J. Vaglica ,  Roy Shor ,  Somvir Dahiya ,  Ori Goren ,  Avraham Horn ,  Arvind Kaushik ,  Arindam Sinha ,  Puneet Wadhawan

IPC: H04M1/00 ,  H04W88/08

CPC classification number: H04W88/085

Abstract: A method and apparatus automatically controls the insertion of information flow data over a shared CPRI link (561) by providing a hardware control mechanism (504-509) at a local radio base station subsystem (501) connected in a CPRI daisy chain configuration between a downstream RE device (570) and an upstream REC device (560) for determining whether the control word being transmitted is sourced from a downstream device (e.g., forwarded data from a downstream RE device) or from the local device.

Abstract translation: 一种方法和装置通过在以CPRI菊花链配置连接的本地无线电基站子系统（501）处提供硬件控制机制（504-509）来自动控制通过共享CPRI链路（561）插入信息流数据， 下游RE设备（570）和上游REC设备（560），用于确定正在发送的控制字是源自下游设备（例如，来自下游RE设备的转发数据）还是来自本地设备。

公开(公告)号：US09391572B2

公开(公告)日：2016-07-12

申请号：US14300701

申请日：2014-06-10

Applicant: Freescale Semiconductor, Inc.

Inventor： Joseph Staudinger

IPC: H03F3/68 ,  H03F3/72 ,  H03F1/02 ,  H03F3/193 ,  H03F3/21 ,  H03F3/217 ,  H03F3/345

CPC classification number: H03F3/72 ,  H03F1/0261 ,  H03F3/193 ,  H03F3/211 ,  H03F3/2171 ,  H03F3/2175 ,  H03F3/345 ,  H03F2200/36 ,  H03F2200/451 ,  H03F2200/537 ,  H03F2203/21151

Abstract: The embodiments described herein provide a radio frequency (RF) driver amplifier and method of operation. In general, the driver amplifier facilitates high performance operation in RF devices while being implemented with only n-type transistors. Using only n-type transistors in the driver amplifier can increase the operating bandwidth of the driver amplifier. Furthermore, using only n-type transistors in the driver amplifier can simplify device fabrication. The driver amplifiers and methods described herein can be used in a variety of applications. As one specific example the driver amplifier can be used in a switch-mode power amplifier (SMPA). Such a SMPA can be configured to amplify a time varying signal, such as an RF.

Abstract translation: 这里描述的实施例提供射频（RF）驱动放大器和操作方法。 通常，驱动放大器便于在仅使用n型晶体管的情况下实现RF器件的高性能操作。 在驱动放大器中仅使用n型晶体管可以增加驱动放大器的工作带宽。 此外，在驱动放大器中仅使用n型晶体管可以简化器件制造。 这里描述的驱动器放大器和方法可以用于各种应用中。 作为一个具体示例，驱动器放大器可以用在开关模式功率放大器（SMPA）中。 这样的SMPA可被配置成放大时变信号，例如RF。

公开(公告)号：US09390278B2

公开(公告)日：2016-07-12

申请号：US13616922

申请日：2012-09-14

Applicant: Ross S. Scouller ,  Daniel L. Andre ,  Jeffrey C. Cunningham

Inventor： Ross S. Scouller ,  Daniel L. Andre ,  Jeffrey C. Cunningham

IPC: G06F12/14 ,  G06F21/62 ,  G06F21/79

CPC classification number: G06F21/6218 ,  G06F12/1466 ,  G06F12/1483 ,  G06F21/79

Abstract: Methods and systems are disclosed for code protection in non-volatile memory (NVM) systems. Information stored within NVM memory sectors, such as boot code or other code blocks, is protected using lockout codes and lockout keys written in program-once memory areas within the NVM systems. Further, lockout codes can be combined into a merged lockout code that can be stored in a merged protection register. The merged protection register is used to control write access to protected memory sectors. Lockout code/key pairs are written to the program-once area when a memory sector is protected. The program-once area, which stores the lockout code/key pairs, is not readable by external users. Once protected, a memory sector can not be updated without the lockout code/key pair.

Abstract translation: 公开了用于非易失性存储器（NVM）系统中的代码保护的方法和系统。 存储在NVM存储器扇区内的信息（例如引导代码或其他代码块）使用在NVM系统中的程序一次存储区中写入的锁定代码和锁定密钥进行保护。 此外，锁定码可以组合成可以存储在合并保护寄存器中的合并锁定码。 合并的保护寄存器用于控制对受保护的存储器扇区的写访问。 当保护存储器扇区时，锁定代码/密钥对被写入到程序一次区域。 存储锁定代码/密钥对的程序一次区域不能被外部用户读取。 一旦被保护，如果没有锁定代码/密钥对，则无法更新存储器扇区。

公开(公告)号：US20160195454A1

公开(公告)日：2016-07-07

申请号：US14588521

申请日：2015-01-02

Applicant: William E. Edwards ,  Michael R. Garrard

Inventor： William E. Edwards ,  Michael R. Garrard

IPC: G01M15/04 ,  G01K7/42

CPC classification number: G01K7/42 ,  G01K7/18 ,  G01K13/08

Abstract: A system for determining a temperature of a first portion of an engine, and related circuit, and related method of operation, are disclosed. In one example embodiment, the system includes a wheel having a plurality of magnetic teeth, and an electrical circuit including a variable reluctance sensor (VRS) including at least one winding, the VRS being positioned proximate the wheel, where the VRS is in thermal contact with the first portion, and a comparator having first and second input terminals and an output terminal, where the comparator is configured to output an output signal at the output terminal. Either the output signal or a further signal generated by the electrical circuit is at least indirectly indicative of a resistance of the at least one winding, whereby an indication of the temperature of the first portion can be determined based upon the output signal or further signal.

Abstract translation: 公开了一种用于确定发动机的第一部分的温度的系统及相关电路及相关的操作方法。 在一个示例性实施例中，系统包括具有多个磁齿的车轮，以及包括至少一个绕组的可变磁阻传感器（VRS）的电路，VRS位于车轮附近，其中VRS处于热接触 第一部分和比较器具有第一和第二输入端子和输出端子，其中比较器被配置为在输出端子处输出输出信号。 输出信号或由电路产生的另外的信号至少间接地指示至少一个绕组的电阻，由此可以基于输出信号或其它信号来确定第一部分的温度的指示。

公开(公告)号：US09386688B2

公开(公告)日：2016-07-05

申请号：US12945825

申请日：2010-11-12

Applicant: James MacDonald ,  William McKinzie, III ,  Walter Parmon ,  Lawrence Rubin

Inventor： James MacDonald ,  William McKinzie, III ,  Walter Parmon ,  Lawrence Rubin

IPC: H01Q1/52 ,  H05K1/02 ,  H01L23/552 ,  H01L23/66 ,  H01Q1/22 ,  H01Q1/32 ,  H01Q9/04 ,  H01Q13/18 ,  H01Q15/00 ,  H01L23/00 ,  H05K1/18

CPC classification number: H05K1/0236 ,  H01L23/552 ,  H01L23/66 ,  H01L24/13 ,  H01L24/16 ,  H01L2223/6627 ,  H01L2223/6677 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/01019 ,  H01L2924/14 ,  H01L2924/1421 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/167 ,  H01Q1/2283 ,  H01Q1/3233 ,  H01Q9/0407 ,  H01Q13/18 ,  H01Q15/0086 ,  H05K1/095 ,  H05K1/116 ,  H05K1/165 ,  H05K1/167 ,  H05K1/181 ,  H05K2201/0329 ,  H05K2201/09072 ,  H05K2201/094 ,  H05K2201/09454 ,  Y10T29/49016 ,  H01L2924/00

Abstract: An integrated antenna package includes an interposer, an integrated circuit die, and a cap that forms a cavity within the integrated antenna package. A lossy ERG structure resides at the cap overlying the integrated circuit device. A lossless EBG structure resides at the cap overlying a microstrip feedline. A radar module includes a plurality of receive portions, each receive portion including a parabolic structure having a reflective surface, an absorber structure, a lens, and an antenna.

Abstract translation: 集成天线封装包括内插器，集成电路管芯和在集成天线封装内形成空腔的盖。 有损的ERG结构位于覆盖集成电路器件的盖子上。 无损的EBG结构位于覆盖微带馈线的帽子上。 雷达模块包括多个接收部分，每个接收部分包括具有反射表面的抛物线结构，吸收体结构，透镜和天线。

公开(公告)号：US09384842B1

公开(公告)日：2016-07-05

申请号：US14717153

申请日：2015-05-20

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Anirban Roy ,  Tom D. Vo

IPC: G11C16/04 ,  G11C16/14 ,  G11C16/34 ,  G11C16/16

CPC classification number: G11C16/14 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/345 ,  G11C16/3472

Abstract: A method of erasing a plurality of non-volatile memory (NVM) cells on a die includes applying erase signals to the plurality of NVM cells. A subset of the plurality of NVM cells is identified to be soft programmed. Information is identified from a non-volatile storage location that stores a value to identify a particular magnitude from a plurality of possible magnitudes of a starting voltage. A soft program signal is applied to the NVM cells identified for soft programming, wherein the starting voltage of the soft program signal has the particular magnitude.

Abstract translation: 擦除芯片上的多个非易失性存储器（NVM）单元的方法包括向多个NVM单元施加擦除信号。 多个NVM单元的子集被识别为软编程。 从非易失性存储位置识别信息，其存储从起始电压的多个可能幅度识别特定幅度的值。 软编程信号被施加到被识别用于软编程的NVM单元，其中软程序信号的起始电压具有特定的大小。