公开(公告)号：US20160111517A1

公开(公告)日：2016-04-21

申请号：US14519068

申请日：2014-10-20

申请人： SANDISK 3D LLC

发明人： Wei-Te Wu ,  Ming-Che Wu ,  Yung-Tin Chen

IPC分类号： H01L29/66 ,  H01L21/311 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/51 ,  H01L27/115 ,  H01L29/786 ,  H01L21/02

CPC分类号： H01L29/6675 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/31111 ,  H01L21/823885 ,  H01L27/0688 ,  H01L27/101 ,  H01L27/11526 ,  H01L27/11573 ,  H01L27/2454 ,  H01L27/249 ,  H01L29/4908 ,  H01L29/4916 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/66484 ,  H01L29/66666 ,  H01L29/78648 ,  H01L45/04 ,  H01L45/06 ,  H01L45/08 ,  H01L45/1226 ,  H01L45/141 ,  H01L45/146 ,  H01L45/16

摘要： Methods for forming a dual gate structure for a vertical TFT are described. The dual gate structure may be formed by performing a first etching process that includes forming a first set of trenches by etching a first set of oxide pillars to a first depth and forming a second set of trenches by etching a second set of oxide pillars to a second depth higher than the first depth, forming a first set of gate structures within the first set of trenches, forming a second set of gate structures within the second set of trenches, performing a second etching process that includes forming a third set of trenches by etching the first set of gate structures from a second initial depth to a third depth and forming a fourth set of trenches by etching the second set of gate structures to a fourth depth higher than the third depth.

摘要翻译： 描述了用于形成用于垂直TFT的双栅极结构的方法。 可以通过执行第一蚀刻工艺来形成双栅极结构，所述第一蚀刻工艺包括通过将第一组氧化物柱蚀刻到第一深度并形成第二组沟槽来形成第一组沟槽，并通过将第二组氧化物柱蚀刻到 第二深度高于第一深度，在第一组沟槽内形成第一组栅极结构，在第二组沟槽内形成第二组栅极结构，执行第二蚀刻工艺，其包括通过以下步骤形成第三组沟槽： 将第一组栅极结构从第二初始深度蚀刻到第三深度，并通过将第二组栅极结构蚀刻到高于第三深度的第四深度而形成第四组沟槽。

公开(公告)号：US20160111513A1

公开(公告)日：2016-04-21

申请号：US14984688

申请日：2015-12-30

申请人： STMicroelectronics, Inc. ,  GlobalFoundries Inc. ,  International Business Machines Corporation

发明人： Qing Liu ,  Ruilong Xie ,  Chun-chen Yeh ,  Xiuyu Cai

IPC分类号： H01L29/423 ,  H01L29/165 ,  H01L29/06 ,  H01L29/16 ,  H01L29/786 ,  H01L29/66

CPC分类号： H01L29/42392 ,  B82Y10/00 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/1037 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/36 ,  H01L29/42364 ,  H01L29/51 ,  H01L29/518 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/6681 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78696

摘要： A high performance GAA FET is described in which vertically stacked silicon nanowires carry substantially the same drive current as the fin in a conventional FinFET transistor, but at a lower operating voltage, and with greater reliability. One problem that occurs in existing nanowire GAA FETs is that, when a metal is used to form the wraparound gate, a short circuit can develop between the source and drain regions and the metal gate portion that underlies the channel. The vertically stacked nanowire device described herein, however, avoids such short circuits by forming insulating barriers in contact with the source and drain regions, prior to forming the gate. Through the use of sacrificial films, the fabrication process is almost fully self-aligned, such that only one lithography mask layer is needed, which significantly reduces manufacturing costs.

摘要翻译： 描述了一种高性能GAA FET，其中垂直堆叠的硅纳米线在传统的FinFET晶体管中承载与鳍片基本上相同的驱动电流，但是在较低的工作电压下并且具有更高的可靠性。 在现有的纳米线GAA FET中出现的一个问题是当金属用于形成环绕栅极时，在源极和漏极区域之间以及在通道下方的金属栅极部分发生短路。 然而，本文所述的垂直堆叠的纳米线器件在形成栅极之前通过形成与源极和漏极区域接触的绝缘屏障来避免这种短路。 通过使用牺牲膜，制造工艺几乎完全自对准，使得仅需要一个光刻掩模层，这显着降低制造成本。

公开(公告)号：US20160111428A1

公开(公告)日：2016-04-21

申请号：US14971026

申请日：2015-12-16

申请人： Ju-Youn Kim ,  Hyung-Soon Jang ,  Jong-Mil Youn ,  Tae-Won Ha

发明人： Ju-Youn Kim ,  Hyung-Soon Jang ,  Jong-Mil Youn ,  Tae-Won Ha

IPC分类号： H01L27/092 ,  H01L29/51 ,  H01L29/49 ,  H01L29/06

CPC分类号： H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823871 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0642 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/161 ,  H01L29/165 ,  H01L29/20 ,  H01L29/42364 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517

摘要： A semiconductor device includes a substrate including a first active region, a second active region and a field region between the first and second active regions, and a gate structure formed on the substrate to cross the first active region, the second active region and the field region. The gate structure includes a p type metal gate electrode and an n-type metal gate electrode directly contacting each other, the p-type metal gate electrode extends from the first active region less than half way toward the second active region.

公开(公告)号：US09318595B2

公开(公告)日：2016-04-19

申请号：US14165021

申请日：2014-01-27

申请人： SK hynix Inc.

发明人： Seung-Mi Lee ,  Yun-Hyuck Ji ,  Beom-Yong Kim ,  Bong-Seok Jeon

IPC分类号： H01L29/78 ,  H01L21/265 ,  H01L29/66 ,  H01L29/10 ,  H01L29/49 ,  H01L29/51 ,  H01L21/8234 ,  H01L21/8238

CPC分类号： H01L29/78 ,  H01L21/26506 ,  H01L21/823462 ,  H01L21/823807 ,  H01L29/1054 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66651 ,  H01L29/7833

摘要： A method for fabricating a semiconductor device includes ion-implanting germanium into a monocrystalline silicon-containing substrate; forming a gate oxide layer over a surface of the monocrystalline silicon-containing substrate and forming, under the gate oxide layer, a germanium-rich region in which the germanium is concentrated, by performing a plasma oxidation process; and crystallizing the germanium-rich region by performing an annealing process.

摘要翻译： 制造半导体器件的方法包括将锗离子注入到单晶硅的衬底中; 在所述单晶含硅衬底的表面上形成栅极氧化物层，并且在所述栅极氧化物层下，通过进行等离子体氧化处理，形成锗浓缩的锗富集区; 并通过进行退火处理使富锗的区域结晶。

公开(公告)号：US09318507B2

公开(公告)日：2016-04-19

申请号：US14416213

申请日：2013-08-30

申请人： Kobe Steel, Ltd.

发明人： Aya Miki ,  Shinya Morita ,  Hiroshi Goto ,  Hiroaki Tao ,  Toshihiro Kugimiya

IPC分类号： H01L29/51 ,  H01L27/12 ,  H01L29/786 ,  H01L29/40 ,  H01L21/02

CPC分类号： H01L27/1225 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02274 ,  H01L29/408 ,  H01L29/4908 ,  H01L29/51 ,  H01L29/78606 ,  H01L29/7869 ,  H01L29/78696

摘要： Provided is a thin film transistor comprising an oxide semiconductor thin film layer and has a threshold voltage that does not change much due to light, a bias stress or the like, thereby exhibiting excellent stress stability. A thin film transistor of the present invention is provided with: a gate electrode; two or more oxide semiconductor layers that are used as a channel layer; an etch stopper layer for protecting the surfaces of the oxide semiconductor layers; a source-drain electrode; and a gate insulator film interposed between the gate electrode and the channel layer. The metal elements constituting an oxide semiconductor layer that is in direct contact with the gate insulator film are In, Zn and Sn. The hydrogen concentration in the gate insulator film, which is in direct contact with the oxide semiconductor layer, is controlled to 4 atomic % or less.

摘要翻译： 提供了一种薄膜晶体管，其包括氧化物半导体薄膜层，并且具有由于光，偏压应力等而不会变化太大的阈值电压，从而表现出优异的应力稳定性。 本发明的薄膜晶体管设有：栅电极; 用作沟道层的两个或更多个氧化物半导体层; 用于保护氧化物半导体层的表面的蚀刻停止层; 源极 - 漏极电极; 以及插入在栅电极和沟道层之间的栅绝缘膜。 构成与栅极绝缘膜直接接触的氧化物半导体层的金属元素为In，Zn和Sn。 与氧化物半导体层直接接触的栅极绝缘膜的氢浓度被控制在4原子％以下。

公开(公告)号：US09312019B1

公开(公告)日：2016-04-12

申请号：US14644461

申请日：2015-03-11

申请人： Kabushiki Kaisha Toshiba

发明人： Wataru Sakamoto

IPC分类号： G11C11/34 ,  G11C16/26 ,  G11C16/14

CPC分类号： G11C16/26 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/14 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/1095 ,  H01L29/4916 ,  H01L29/495 ,  H01L29/51

摘要： According to an embodiment, an operation method for a memory device which has a first memory element and a second memory element respectively provided on both sides of a semiconductor member includes applying a first voltage to a second word line, the first voltage being negative for a voltage of a cell source line, and applying a second voltage to a first word line, the second voltage being positive for the voltage of the cell source line when reading out a data from the first memory element.

摘要翻译： 根据一个实施例，一种用于存储器件的操作方法，其具有分别设置在半导体部件的两侧的第一存储元件和第二存储元件，包括对第二字线施加第一电压，第一电压为负 电池源线的电压，以及向第一字线施加第二电压，当从第一存储元件读出数据时，第二电压对于电池源线的电压为正。

公开(公告)号：US09293532B2

公开(公告)日：2016-03-22

申请号：US14751542

申请日：2015-06-26

申请人： GLOBALFOUNDRIES INC.

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Pouya Hashemi ,  Ali Khakifirooz ,  Alexander Reznicek

IPC分类号： H01L21/8238 ,  H01L29/06 ,  H01L29/66 ,  H01L51/00 ,  H01L29/49 ,  H01L29/775 ,  H01L29/423 ,  H01L29/51 ,  H01L29/10 ,  H01L29/786 ,  H01L29/08

CPC分类号： H01L29/42392 ,  H01L21/8238 ,  H01L21/82385 ,  H01L29/0649 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78603 ,  H01L29/78606 ,  H01L29/78696 ,  H01L51/0048

摘要： A method for fabricating a semiconductor device comprises forming a nanowire on an insulator layer at a surface of a substrate; forming a dummy gate over a portion of the nanowire and a portion of the insulator layer; forming recesses in the insulator layer on opposing sides of the dummy gate; forming spacers on opposing sides of the dummy gate; forming source regions and drain regions in the recesses in the insulator layer on opposing sides of the dummy gate; depositing an interlayer dielectric on the source regions and the drain regions; removing the dummy gate to form a trench; removing the insulator layer under the nanowire such that a width of the trench underneath the nanowire is equal to or less than a distance between the spacers; and forming a replacement gate in the trench.

公开(公告)号：US20160079395A1

公开(公告)日：2016-03-17

申请号：US14699091

申请日：2015-04-29

申请人： Samsung Electronics Co., Ltd.

发明人： Hyun-Jun SIM ,  Jae-Young PARK ,  Sun-Young LEE

IPC分类号： H01L29/66 ,  H01L29/51 ,  H01L21/28 ,  H01L21/306 ,  H01L21/762

CPC分类号： H01L29/66795 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/0234 ,  H01L21/02351 ,  H01L21/2686 ,  H01L21/28185 ,  H01L21/30604 ,  H01L21/76224 ,  H01L29/165 ,  H01L29/51 ,  H01L29/511 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： In a method of manufacturing a semiconductor device, a preliminary gate insulation layer is formed on a substrate, and at least a portion of the substrate serves as a channel region. A hydrogen plasma treatment is performed on the preliminary gate insulation layer to form a gate insulation layer, and the hydrogen plasma treatment supplying a hydrogen-containing gas and an inert gas supply in a chamber via different gas supply parts to form a hydrogen plasma region and an inert gas plasma region in the chamber, respectively. A gate electrode is formed on the gate insulation layer, and impurity regions are formed at upper portions of the substrate adjacent to the gate electrode.

摘要翻译： 在半导体装置的制造方法中，在基板上形成预备栅极绝缘层，并且至少一部分基板作为沟道区域。 在预备栅极绝缘层上进行氢等离子体处理以形成栅极绝缘层，并且氢等离子体处理通过不同的气体供应部分在室中提供含氢气体和惰性气体源，以形成氢等离子体区域， 室内的惰性气体等离子体区域。 栅电极形成在栅极绝缘层上，杂质区形成在与栅电极相邻的衬底的上部。

公开(公告)号：US09281413B2

公开(公告)日：2016-03-08

申请号：US14165785

申请日：2014-01-28

申请人： Infineon Technologies Austria AG

发明人： Matthias Strassburg ,  Gerhard Prechtl

IPC分类号： H01L29/788 ,  H01L29/16 ,  H01L29/205 ,  H01L29/423 ,  H01L29/51 ,  H01L29/778 ,  H01L29/20

CPC分类号： H01L29/788 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/42324 ,  H01L29/51 ,  H01L29/513 ,  H01L29/518 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/7881

摘要： An enhancement mode device includes a floating gate structure. The floating gate structure includes a first bottom dielectric layer, a second bottom dielectric layer on the first bottom dielectric layer and a conductive floating gate on the second bottom dielectric layer.

摘要翻译： 增强模式装置包括浮动栅极结构。 浮置栅极结构包括第一底部电介质层，第一底部电介质层上的第二底部电介质层和第二底部电介质层上的导电浮动栅极。

公开(公告)号：US09281374B2

公开(公告)日：2016-03-08

申请号：US14490679

申请日：2014-09-19

申请人： UNITED MICROELECTRONICS CORP.

发明人： Tsun-Min Cheng ,  Min-Chuan Tsai ,  Chih-Chien Liu ,  Jen-Chieh Lin ,  Pei-Ying Li ,  Shao-Wei Wang ,  Mon-Sen Lin ,  Ching-Ling Lin

IPC分类号： H01L29/49 ,  H01L29/423 ,  H01L29/43 ,  H01L29/772 ,  H01L29/66 ,  H01L29/78 ,  H01L29/51 ,  H01L21/8238 ,  H01L21/8234

CPC分类号： H01L29/4966 ,  H01L21/82345 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4232 ,  H01L29/435 ,  H01L29/51 ,  H01L29/66045 ,  H01L29/66545 ,  H01L29/78

摘要： A metal gate structure located on a substrate includes a gate dielectric layer, a metal layer and a titanium aluminum nitride metal layer. The gate dielectric layer is located on the substrate. The metal layer is located on the gate dielectric layer. The titanium aluminum nitride metal layer is located on the metal layer.

摘要翻译： 位于基板上的金属栅极结构包括栅介质层，金属层和氮化铝钛金属层。 栅介质层位于衬底上。 金属层位于栅极电介质层上。 氮化铝钛金属层位于金属层上。